SSTFSC Series – 18.3MM X 11.7MM Metal Full Size Dip Stratum 3 CMOS (VC)TCXO
Part Numbering Guide
Electrical Parameters
Parameters | Units | Min | Typical | Max | Remarks |
---|---|---|---|---|---|
Frequency Range | MHz | 2 | 40 | ||
Frequency Tolerance at +25ºC | ppm | -0.3 | +0.3 | ||
Freq. Stability vs. Op Temp. | ppm | -1.0 | +1.0 | See part numbering guide for options. | |
Freq. Stability vs. Supply Voltage | ppm | -0.1 | +0.1 | VDD ±5% Change | |
Freq. Stability vs. Load | ppm | -0.1 | +0.1 | ±5% Change | |
Freq. Stability vs. Aging/Year | ppm | -1.0 | +1.0 | 1 year, ±2.6ppm for 10years | |
Operating Temperature | °C | -40 | +85 | See part numbering guide for options. | |
Storage Temperature | °C | -55 | +125 | ||
Supply Voltage (VDD) - 3.3V Option | V | 3.135 | 3.3 | 3.465 | |
Supply Voltage (VDD) - 5.0V Option | V | 4.750 | 5.0 | 5.250 | |
Current (IDD) | mA | 20 | |||
Current Voltage (VC, VCTCXO) - 3.3V Option | V | 0.3 | 3.0 | ||
Current Voltage (VC, VCTCXO) 5.0V Option | V | 0.5 | 4.5 | ||
Pullability (VCTCXO) | ppm | ±5.0 | ±12.0 | See part numbering guide for options. | |
Linearity (VCTCXO) | % | 20 | |||
Output Load (CMOS) | pF | 15 | |||
Output Logic Levels High (VOH) | V | 0.9*VDD | |||
Output Logic Levels Low (VOL) | V | 0.1*VDD | |||
Rise (TR) and Fall (TF) Time | ns | 10 | |||
Symmetry (Duty Cycle) | % | 40 | 50 | 60 | |
Start-Up Time | ms | 10 | |||
Frequency Adjustment | ppm | 3 | |||
Phase Noise (Typical) 10Hz Offset | dBc/Hz | -80 | |||
Phase Noise (Typical) 100Hz Offset | dBc/Hz | -120 | |||
Phase Noise (Typical) 1KHz Offset | dBc/Hz | -135 | |||
Phase Noise (Typical) 10KHz Offset | dBc/Hz | -140 | |||
Phase Noise (Typical) 100KHz Offset | dBc/Hz | -145 |
Outline Drawing & Recommended Landed Pattern
All dimensions are in millimeters (mm) unless otherwise noted. Drawings are not to scale.