SLO75P Series – 7.0MM X 5.0MM Ceramic SMD Low Current 6 Pad LVPECL Oscillator

3D Product View

3D View

Features

• ±20ppm (Frequency Stability) Available
• Ceramic Package
• LVPECL
• Low Current Consumption
• Fundamental or 3rd Overtone Crystal

Applications

• Fiber Channel
• Gigabit Ethernet
• PCI Express

3D Product View

3D View

Features

• ±20ppm (Frequency Stability) Available
• Ceramic Package
• LVPECL
• Low Current Consumption
• Fundamental or 3rd Overtone Crystal

Applications

• Fiber Channel
• Gigabit Ethernet
• PCI Express

Part Number Builder

Please choose your parameters to build a part number:

Part Numbering Guide

SLO75P-part-numbering-guide-updated

Electrical Parameters

ParametersUnitsMinTypicalMaxRemarks
Frequency RangeMHz100320135~175MHz(1.8V), 100~320MHz(2.5&3.3V)
Frequency Stability (Includes Initial
Tolerance at 25°C, Frequency Stability
over Operating Temperature, Output Load
Change, Supply Voltage Change, and First
Year Aging at 25°C.)
ppm-20+20See part numbering guide for options.
Operating Temperature°C-40+85See part numbering guide for options.
Storage Temperature°C-55+125
Supply Voltage (VDD) - 2.5V OptionV2.3752.52.625
Supply Voltage (VDD) - 3.3V OptionV3.1353.33.465
Current (IDD)mA50
Output Load ((LVPECL)5050 Ω into VDD-2.0VDC
Output Logic Levels High (VOH at 2.5V)V1.4151.760
Output Logic Levels Low (VOL at 2.5V)V0.6701.195
Output Logic Levels High (VOH at 3.3V)V2.2152.420
Output Logic Levels Low (VOL at 3.3V)V1.4701.745
Rise (TR) and Fall (TF) Timens0.150.3Measured at 20% to 80% of Waveform
Symmetry (Duty Cycle)%455055
Tri-State Input Voltage - EnableV0.7*VDDNo Connection
Tri-State Input Voltage - DisableV0.3*VDD
Start-Up Timems5
Phase Jitter (12kHz ~ 20MHz)ps0.120.15

Outline Drawing & Recommended Landed Pattern

All dimensions are in millimeters (mm) unless otherwise noted. Drawings are not to scale.

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