Understanding Power Good Signals in PMIC Design

PGOOD monitoring depends on high-precision voltage comparator circuits integrated directly within power ICs or external supervisory devices. These circuits continuously compare a feedback or sense voltage (typically the output divided down by a resistor network) against an internal reference^[1].

The voltage threshold defines the output level at which the comparator toggles the PGOOD line. Many regulators assert PGOOD once the output rises to roughly 90% to 95% of nominal and de-assert it if the rail falls below roughly 88% to 92%. For example, one TI buck converter releases PGOOD when its feedback voltage is between 91% and 106% of the internal reference and pulls it low below 89% or above 108%^[1]. Another uses a −6%/+7% good window with −8%/+9% fault thresholds^[2]. UTC’s UD052012 synchronous buck converter releases its open-drain PG pin once the output rises above 90% of nominal and actively holds it low during soft-start, standby, and shutdown^[13]. Always confirm the exact values in your device’s datasheet. Threshold accuracy also varies. Dedicated window supervisors can hold their thresholds to within about ±1% over temperature^[4], which is why high-reliability designs often pair a regulator’s built-in PGOOD with an external supervisor. Many regulators and PMICs also include an upper (overvoltage) threshold, typically around 105% to 110% of nominal, so PGOOD also drops if the rail rises too high^[1][2].

Power rails do not reach target operating voltages instantaneously; they exhibit rise times influenced by soft-start settings and load capacitance. To prevent premature execution during voltage ringing or initial overshoot, PGOOD circuits incorporate built-in delay and debounce timers. Once the output voltage crosses the valid threshold, an internal timer holds PGOOD low for a delay period (t_DELAY). Regulators with built-in PGOOD often use short, fixed delays. One TI buck converter, for example, waits 272 switching cycles before releasing PGOOD^[1]. Standalone supervisors and system-level power supply units may use much longer delays. The Intel ATX power supply design guide, for instance, calls for at least 100 ms between the rails stabilizing and PWR_OK asserting^[5]. Dedicated PC power supply supervisors build this kind of delay in. UTC’s 3513, for example, specifies a 300 ms typical delay (200 ms to 490 ms) between its power-good input and its open-drain power-good output^[14]. Many devices also filter the falling edge so that brief ripple or transients don’t cause false fault indications^[1]. Together, these delays give the rail time to stabilize before downstream components begin to operate.

In systems containing complex processors, high-performance FPGAs, or multi-stage analog circuits, the device datasheet often specifies a required or recommended power-up order^[7]. Turning on core, I/O, and memory rails in the wrong order can cause excessive inrush current, forward-bias internal protection diodes, trigger latch-up, or leave I/Os in an undefined state^[7][9].

The simplest hardware technique for controlling start-up order is event-based power sequencing, achieved by chaining the PGOOD signal of an upstream supply directly to the enable (EN) pin of the next downstream regulator.

1. Stage 1 Activation: The primary supply (e.g., a 5.0 V bus regulator) starts up.
2. Voltage Verification: The primary regulator output reaches nominal voltage, and its internal timer satisfies t_DELAY.
3. Trigger Downstream: The primary regulator asserts its PGOOD pin HIGH.
4. Stage 2 Activation: Because the PGOOD pin connects directly to the Enable pin of the secondary regulator (e.g., a 1.8 V supply), the secondary rail begins its soft-start ramp.
5. System Readiness: The process repeats through subsequent stages in the order specified by the load device’s datasheet. Note that many devices require the core rail first. AMD’s Artix-7 FPGAs, for example, recommend VCCINT, then VCCBRAM, VCCAUX, and finally VCCO^[7].

This cascade approach enforces start-up order in hardware without microcontroller timing loops^[8]. It has limits, however. A simple PGOOD-to-EN chain doesn’t control power-down order, so designs with strict shutdown requirements typically use a dedicated power sequencing IC^[8][9].

Some regulators go a step beyond a simple PGOOD flag. 3PEAK’s TPP20608x family of 17 V, 6 A synchronous buck converters pairs an open-drain power-good output with a soft-start function that can be set by an external resistor or configured for sequencing and tracking mode, giving designers control over both the order and the ramp of each rail^[15].

Integrating a power good output into a broader digital system requires careful consideration of board-level pin logic and electrical interface characteristics.

PMICs and discrete regulators deliver PGOOD signals using one of two primary output topologies: open-drain or push-pull. Selecting the correct interface type determines how the signal will connect to host controllers.

• Open-Drain Outputs: An open-drain PGOOD pin uses an internal N-channel MOSFET that connects the output to ground when power is not good, provided the IC has enough bias to drive that MOSFET (see Common PGOOD Design Mistakes, below)^[3]. When the power rail reaches specification, the internal MOSFET turns off, leaving the output high-impedance. This topology requires an external pull-up resistor connected to a valid logic supply rail. Open-drain outputs offer significant flexibility, as they allow wired-AND connections where multiple PGOOD pins pull down a single common line. They also enable level-shifting, allowing a regulator running on a 5 V input to drive a 3.3 V or 1.8 V microcontroller input pin safely^[10].
• Push-Pull Outputs: Push-pull outputs feature both internal P-channel and N-channel transistors, allowing the driver to actively source current HIGH or sink current LOW. Push-pull pins do not require external pull-up resistors, reducing overall component counts. However, push-pull pins cannot be tied directly together in a multi-rail wired-AND topology, nor can they adapt output logic voltage levels independently.

Supervisor families often offer both topologies, so you can match the output to the receiving logic. 3PEAK’s TPV803, TPV809, and TPV810, for instance, share the same 200 ms typical reset timeout, but the TPV803 uses an open-drain, active-low output that needs a pull-up resistor, while the TPV809 (active-low) and TPV810 (active-high) use push-pull outputs^[17].

When connecting an open-drain PGOOD output to an interrupt pin on a host processor, choose the pull-up resistor carefully. Values commonly fall between 10 kΩ and 100 kΩ^[1]. Lower values give faster rise times but draw more current whenever PGOOD is low. Also confirm that the pull-up voltage doesn’t exceed the PGOOD pin’s absolute maximum rating^[1].

On low-voltage converters, that limit is often tied to the input supply. UTC’s UD052012, for example, rates its PG pin only up to V_IN, so the pull-up rail must not exceed the converter’s input voltage^[13].

Despite the apparent simplicity of PGOOD status lines, subtle design oversight can cause unreliable hardware behavior. Avoid these common design pitfalls:

Suntsu supplies power management ICs from UTC (Unisonic Technologies) and 3PEAK, two manufacturers whose portfolios cover the PGOOD functions discussed above, from regulators with built-in power-good outputs to standalone supervisors.

Pairing a regulator’s built-in PGOOD with a standalone supervisor from either line is a practical way to apply the layered monitoring approach described earlier: the regulator flags its own rail, while the supervisor provides a tighter, independently timed reset for the processor.