EN25SX128A-104HIP(2PC)

128Mb SPI NOR Flash Ind.
Part Description

128 Mbit SPI NOR Flash, 104 MHz, Industrial

Quantity 1,239 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerESMT
Manufacturing StatusMP
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package8-pin SOP 200milMemory FormatNOR FlashTechnologySPI NOR Flash
Memory Size128 MbitAccess Time8 nsGradeIndustrial
Clock Frequency104 MHzVoltage2.5VMemory TypeNon-Volatile
Operating Temperature-40°C – 85°CWrite Cycle Time Word Page3 msPackaging8-pin SOP 200mil
Mounting MethodSurface MountMemory InterfaceParallelMemory Organization16M x 8
Moisture Sensitivity Level3RoHS ComplianceCompliantREACH ComplianceREACH Unknown
QualificationN/AECCNEAR99HTS Code8542.32.00.71

Overview of EN25SX128A-104HIP(2PC) – 128 Mbit SPI NOR Flash, 104 MHz, Industrial

The EN25SX128A-104HIP(2PC) is a 128 M-bit serial SPI NOR Flash memory device designed for embedded code and data storage in industrial systems. It implements a serial interface architecture with Standard, Dual and Quad SPI I/O and supports high-speed Fast Read at a 104 MHz clock rate for Single/Dual/Quad I/O.

With single-supply operation over a 1.65–1.95 V range, uniform sector architecture, and industry-grade temperature support, the device targets applications requiring field-updatable code, flexible erase/program granularity, and reliable non-volatile storage.

Key Features

  • Memory Capacity & Organization — 128 M-bit serial flash organized as 16,384 KByte with 65,536 pages and 256 bytes per programmable page, enabling fine-grained page programming.
  • High‑speed SPI I/O — Supports Standard, Dual and Quad SPI modes with a 104 MHz clock rate for Fast Read operations to accelerate code and data access.
  • Power Supply — Single power supply operation with a full voltage range of 1.65–1.95 V as specified in the device datasheet.
  • Program / Erase Performance — Typical page program time 0.5 ms, sector erase time 40 ms, block/half-block erase times and full chip erase time documented for system planning.
  • Flexible Erase Architecture — Uniform sector/block architecture with 4,096 × 4-Kbyte sectors, 512 × 32-Kbyte blocks and 256 × 64-Kbyte blocks for targeted erase operations.
  • Data Integrity & Security — Lockable 3 × 512-byte One-Time-Programmable (OTP) security sector, Read Unique ID support and volatile status register bits for control and protection.
  • Low Power Operation — Typical active current 4.5 mA and deep power-down current as low as 0.1 µA for energy-conscious designs.
  • Endurance & Retention — Minimum 100k program/erase cycles per sector/block and data retention beyond 20 years as specified for long-term reliability.
  • Package & Temperature — Available in an 8‑lead SOP 200 mil package (specified for this part) and rated for industrial temperature range (‑40 °C to 85 °C).
  • Hardware/Software Protection — WP#, HOLD# pins and software protection features allow selective block protection, write suspend/resume and configurable protection schemes.

Typical Applications

  • Field‑upgradeable Embedded Firmware — Store and update application code where selective block unprotect/modify operations are required for patches and firmware revisions.
  • Non‑volatile Data Storage — Maintain persistent configuration and data segments with long retention and high erase/program endurance.
  • Boot and System Code — Fast SPI read performance at 104 MHz supports reliable boot code and execution-in-place scenarios in industrial controllers.

Unique Advantages

  • Quad‑I/O Performance: Quad SPI support plus a 104 MHz Fast Read clock rate deliver higher throughput for code and data fetch.
  • Granular Erase Control: 4 KB sectors and larger block sizes let designers minimize erase scope and reduce update time and wear on critical regions.
  • Robust Protection Mechanisms: Lockable OTP sector, hardware WP#/HOLD# control and software protection allow flexible and secure memory management.
  • Low‑power Footprint: Typical active and power‑down currents (4.5 mA / 0.1 µA) help reduce system power during active and standby states.
  • Industrial Reliability: Specified for an industrial temperature range and a minimum of 100k program/erase cycles to support long lifecycle deployments.
  • Clear Scalability: Uniform sector architecture and SFDP signature support make the device suitable for systems requiring predictable memory layout and discoverability.

Why Choose EN25SX128A-104HIP(2PC)?

The EN25SX128A-104HIP(2PC) combines high-speed SPI I/O, flexible erase/program granularity and robust protection features in an industrial-grade serial NOR Flash package. Its Quad SPI capability and 104 MHz fast-read support enable responsive code and data access while providing long-term endurance and retention for deployed systems.

This device is well suited for embedded designs that require field-updateable firmware, secure storage segments and predictable erase behavior. With low-power modes, hardware/software protection and an industry temperature rating, it offers a balanced option for industrial firmware storage and non‑volatile data applications.

Request a quote or submit an inquiry to evaluate EN25SX128A-104HIP(2PC) for your next embedded design and to confirm availability, packaging options, and ordering quantities.

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