AT6003A-4AC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 120 1600 144-LQFP |
|---|---|
| Quantity | 1,136 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 144-LQFP (20x20) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 144-LQFP | Number of I/O | 120 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 1600 | ||
| Number of Gates | 9000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6003A-4AC – AT6000(LV) Field Programmable Gate Array (FPGA), 1,600 Cells, 120 I/O, 144-LQFP
The AT6003A-4AC is an SRAM-based FPGA from the AT6000(LV) series designed for reconfigurable coprocessors and compute‑intensive logic. The device implements a symmetrical array architecture with a flexible busing network and programmable I/O, enabling adaptive hardware and hardware acceleration in high‑speed digital systems.
This device delivers system speeds greater than 100 MHz and supports in‑system reconfiguration without loss of data or machine state, making it suitable for designs that require field programmability and runtime adaptability.
Key Features
- Core Capacity — 1,600 logic element cells and approximately 9,000 usable gates provide the building blocks for mid‑density FPGA designs.
- Performance — System speeds greater than 100 MHz with flip‑flop toggle rates above 250 MHz. Input delays of 1.2 ns/1.5 ns and output delays of 3.0 ns/6.0 ns support high‑speed timing requirements.
- I/O — 120 user I/Os with independently configurable TTL/CMOS input thresholds, open‑collector/tristate outputs, programmable slew‑rate control, and 16 mA drive per I/O (combinable up to 64 mA).
- Power and Voltage — Operates at 5.0 V (VCC = 4.75 V to 5.25 V). Very low standby current (500 μA / 200 μA) and typical operating current for this device class listed at 25–45 mA.
- Architecture & Reconfiguration — Symmetrical grid of cells with local and express busing, independently controlled column clocks and resets, and complete/partial in‑system reconfiguration without loss of data or machine state.
- Clocking — Independently controlled column clocks and resets with clock skew less than 1 ns across the chip to support synchronous designs.
- Package & Temperature — 144‑LQFP (20 × 20 mm) surface‑mount package; commercial operating temperature range 0 °C to 70 °C.
- Compliance — RoHS compliant.
Typical Applications
- Reconfigurable Coprocessors — Implement hardware acceleration blocks and offload compute‑intensive tasks using the device’s array and reconfiguration capabilities.
- Hardware Acceleration — Cache logic and adaptive hardware implementations to accelerate algorithms in real time.
- High‑Speed Digital Systems — Systems requiring >100 MHz operation and fine timing control benefit from the device’s performance and low clock skew.
Unique Advantages
- Adaptive In‑System Reconfiguration: Complete and partial reconfiguration without loss of data or machine state enables live updates and field upgrades.
- Balanced Performance and Density: 1,600 logic element cells and ~9,000 usable gates provide a mid‑range capacity for compute‑intensive logic while keeping board area and power modest.
- Flexible I/O: Independently configurable I/O with TTL/CMOS thresholds, programmable slew‑rate, and strong drive options simplify interfacing with a wide range of peripherals.
- Low Power Standby and Moderate Operating Current: Very low standby currents and typical operating currents in the tens of milliamps help designs meet power budgets.
- Deterministic Clocking: Independently controlled column clocks and resets with <1 ns skew support tightly synchronized architectures.
- Industry‑Standard Package: 144‑LQFP (20 × 20 mm) surface‑mount package eases PCB layout and thermal considerations for commercial applications.
Why Choose AT6003A-4AC?
The AT6003A-4AC positions itself as a practical, mid‑density FPGA option for engineers needing reconfigurable coprocessing and hardware acceleration at system speeds above 100 MHz. Its symmetrical cell array, flexible busing network, and in‑system reconfiguration support enable adaptable designs that can be updated in the field without losing state.
With 1,600 logic element cells, 120 user I/Os, configurable I/O standards and drive, RoHS compliance, and a commercial temperature range, this device fits a range of high‑speed embedded designs where performance, reconfigurability, and manageable power consumption are required. Pin location consistency across the AT6000 series also supports design scalability within the family.
Request a quote or contact sales to check availability, pricing, and technical support for the AT6003A-4AC.

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