AT6005-2AC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 80 3136 100-TQFP |
|---|---|
| Quantity | 1,776 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 80 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 3136 | ||
| Number of Gates | 15000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6005-2AC – AT6000(LV) Field Programmable Gate Array (FPGA) IC 80 3136 100-TQFP
The AT6005-2AC is an SRAM-based FPGA from Microchip Technology in the AT6000(LV) family. The device provides a symmetrical cell array architecture and flexible busing network intended for reconfigurable logic and compute-intensive functions. With 3,136 logic elements and approximately 15,000 usable gates, this commercial-grade, surface-mount FPGA targets applications that require mid-density programmable logic with discrete I/O and predictable power and packaging specifications.
Key Features
- Core Logic 3,136 logic elements (cells) delivering roughly 15,000 usable gates and up to 3,136 registers for implementing combinational and registered logic.
- Performance Series-level characteristics include system speeds greater than 100 MHz and flip-flop toggle rates above 250 MHz; specified input and output delays are listed in the datasheet.
- I/O System 80 user I/Os on this device with independently configurable I/O options from the AT6000(LV) series — TTL/CMOS input thresholds, open-collector/tristate output modes, programmable slew-rate control, and 16 mA drive per I/O (combinable to 64 mA).
- Configuration and Architecture SRAM-based, sectorized symmetrical array with a local and express busing network; supports complete/partial in-system reconfiguration and cache-logic design for adaptive hardware implementations.
- Power Supports 5.0 V operation (VCC = 4.75 V to 5.25 V). Series-level power figures include low standby currents and typical operating currents specified in the datasheet.
- Package & Mounting 100-TQFP (14 × 14) surface-mount package, commercial grade, RoHS compliant; operating temperature range 0 °C to 70 °C.
- Reliability & Test Devices in the AT6000 family are manufactured on a 0.6 µm CMOS process and are 100% factory-tested as described in the series documentation.
Typical Applications
- Reconfigurable Coprocessors Mid-density logic and high toggle-rate capability make the AT6005-2AC suitable for hardware acceleration and offloading compute-intensive functions from a host processor.
- Interface Bridge and Glue Logic With 80 configurable I/Os and programmable drive/slew options, the device is useful for custom protocol bridging, bus interfacing, and peripheral control.
- Prototyping and Adaptive Logic SRAM-based in-system reconfiguration supports iterative development and adaptive hardware designs where function can be updated without component replacement.
- Control and Timing Functions Independently controlled column clocks and resets and low clock skew across the array support deterministic timing for control, sequencing, and real-time logic tasks.
Unique Advantages
- Mid-density integration: 3,136 logic elements and ~15,000 gates provide substantial logic capacity while keeping board-level complexity and BOM impact manageable.
- Flexible I/O configuration: Programmable thresholds, output modes and slew-rate control let you adapt drive and signaling to a wide range of external devices and interfaces.
- In-system reconfiguration: Complete/partial reconfiguration enables firmware-like updates to hardware logic without removing the device, supporting field updates and iterative designs.
- Predictable power and supply: Defined 5.0 V supply range (4.75 V to 5.25 V) and series-level operating current figures assist in power budgeting and system design.
- Standard packaging and mount: 100-TQFP (14 × 14) surface-mount package simplifies placement on standard PCBs and supports automated assembly.
Why Choose AT6005-2AC?
The AT6005-2AC combines mid-range logic capacity with the architectural flexibility of the AT6000(LV) family, delivering a practical balance of performance, I/O configurability, and reprogrammability for embedded designs. Its symmetrical cell array, local/express busing network, and support for in-system reconfiguration make it appropriate for designs that require adaptive hardware or compute offload.
This commercial-grade FPGA is suited for engineers designing modular, updateable systems where 3,136 logic elements, 80 user I/Os, and a 100-TQFP package meet board-level and power-supply constraints. The device benefits projects that require defined operating temperature and supply ranges and compliance with RoHS requirements.
Request a quote or submit an inquiry to receive availability and pricing information for the AT6005-2AC.

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