AT6005-2AI
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 80 3136 100-TQFP |
|---|---|
| Quantity | 98 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Industrial | Operating Temperature | -40°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 80 | Voltage | 4.5 V - 5.5 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 3136 | ||
| Number of Gates | 15000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6005-2AI – AT6000(LV) FPGA, 3,136 Logic Elements, 100‑TQFP
The AT6005-2AI is an SRAM-based Field Programmable Gate Array (FPGA) from the AT6000(LV) series designed for reconfigurable coprocessor and compute‑intensive logic implementations. Its symmetrical cell array architecture and programmable I/O make it suitable for designs that require high-speed logic, in-system reconfiguration and adaptable hardware acceleration.
This device delivers series-class performance characteristics such as system speeds greater than 100 MHz and flip‑flop toggle rates above 250 MHz, while supporting industrial operating temperature and a 100‑pin TQFP package for compact surface‑mount integration.
Key Features
- Core Performance — System speeds >100 MHz and flip‑flop toggle rates >250 MHz, with specified input and output delay characteristics for timing‑sensitive designs.
- Logic Capacity — 3,136 logic elements (cells) corresponding to approximately 15,000 usable gates and up to 3,136 registers for implementing medium‑density logic functions.
- I/O and Programmable Interfaces — 80 user I/Os with independently configurable thresholds (TTL/CMOS), open‑collector/tristate options, programmable slew‑rate control and I/O drive of 16 mA (combinable to 64 mA) to match a range of board‑level interface needs.
- Reconfiguration & Adaptive Logic — Supports complete/partial in‑system reconfiguration without loss of data or machine state, enabling adaptive hardware and runtime updates.
- Power — Designed for low power operation with series standby and typical operating currents documented in the AT6000(LV) datasheet; device supply range is 4.5 V to 5.5 V.
- Clocking — Independently controlled column clocks and resets with clock skew less than 1 ns across the chip for deterministic timing across the array.
- Package & Temperature — 100‑TQFP (14 × 14 mm) surface‑mount package; industrial operating temperature range of −40 °C to 85 °C and RoHS compliant.
Typical Applications
- Reconfigurable Coprocessors — Implement hardware acceleration and offload compute‑intensive tasks using the device’s array of logic elements and in‑system reconfiguration.
- High‑Speed Logic and Control — Use for timing‑sensitive control logic and state machines that benefit from the device’s >100 MHz system speeds and low clock skew.
- Adaptive or Upgradeable Hardware — Deploy in systems that require partial reconfiguration or runtime updates without losing machine state.
- Industrial Embedded Systems — Suitable for space‑constrained, temperature‑sensitive environments thanks to the 100‑TQFP package and −40 °C to 85 °C rating.
Unique Advantages
- Reconfigurability at Runtime: Complete or partial in‑system reconfiguration preserves data and state while enabling design updates and adaptive logic.
- Deterministic Clocking: Independently controlled column clocks and resets with sub‑nanosecond skew support reliable timing across the array.
- Flexible I/O Options: Programmable I/O thresholds, output modes and drive strength reduce the need for external level translators and buffers in many interface scenarios.
- Compact, Industry‑Grade Packaging: 100‑TQFP (14×14) surface‑mount package and an industrial temperature range allow deployment in rugged embedded designs.
- Proven Series Architecture: Symmetrical cell array and efficient busing network provide scalable logic density and consistent pin locations for design migration within the AT6000(LV) series.
Why Choose AT6005-2AI?
The AT6005-2AI combines a mid‑range logic capacity (3,136 cells / ~15,000 usable gates) with high‑speed operation and in‑system reconfiguration, making it a practical choice for engineers implementing compute‑intensive or reconfigurable functions in industrial embedded systems. Its programmable I/O, deterministic clocking and compact 100‑TQFP package simplify board integration while supporting adaptive hardware strategies.
Designed as part of the AT6000(LV) family, the AT6005-2AI benefits from a consistent architecture and available development tools for design entry and implementation, enabling smoother migration and development workflows for medium‑density FPGA applications.
Request a quote or submit an RFQ to receive pricing and availability information for the AT6005-2AI.

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