AT6005-4AC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 80 3136 100-TQFP |
|---|---|
| Quantity | 413 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 80 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 3136 | ||
| Number of Gates | 15000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6005-4AC – AT6000(LV) FPGA, 3,136 Cells, 100-TQFP, 80 I/O
The AT6005-4AC is an SRAM-based Field Programmable Gate Array from Microchip Technology's AT6000(LV) family, offering a balanced combination of logic density and I/O capability in a 100-TQFP (14×14) surface-mount package. The device implements a symmetrical grid of logic cells with surrounding programmable I/O, making it well suited for reconfigurable coprocessors and compute-intensive logic.
Designed for high-speed operation, the AT6005-4AC supports system speeds greater than 100 MHz and flip-flop toggle rates above 250 MHz, while providing independently configurable I/O and in-system reconfiguration for adaptive hardware implementations.
Key Features
- Core Architecture Symmetrical array of 3,136 logic cells (registers) implementing approximately 15,000 usable gates, enabling dense logic integration for custom hardware functions.
- Performance Supports system speeds > 100 MHz and flip-flop toggle rates > 250 MHz; input delays around 1.2 ns/1.5 ns and output delays around 3.0 ns/6.0 ns for predictable timing behavior.
- Programmable I/O 80 user I/O pins with independently configurable thresholds (TTL/CMOS), open-collector/tristate outputs, programmable slew-rate control and I/O drive of 16 mA (combinable up to 64 mA) for flexible interface design.
- Reconfiguration Complete and partial in-system reconfiguration capability without loss of data or machine state, enabling field updates and adaptive hardware acceleration.
- Power and Low-Power Modes Typical operating current for the AT6005 device is listed at 40–80 mA, with very low standby currents reported (on the series), supporting energy-conscious designs at a 5.0 V supply (VCC = 4.75 V to 5.25 V).
- Clocking and Timing Independently controlled column clocks and resets with clock skew less than 1 ns across the chip, plus programmable clock options to manage timing domains efficiently.
- Package & Environmental 100-TQFP (14×14) surface-mount package, commercial-grade operation from 0 °C to 70 °C, and RoHS compliant.
Typical Applications
- Reconfigurable Coprocessors: Implement hardware acceleration for compute-intensive tasks, leveraging the device’s dense cell array and high toggle rates.
- Custom Logic and Control: Replace multiple discrete logic components with a single programmable device for control logic, protocol handling, and glue logic in commercial embedded systems.
- Interface Bridging and I/O Expansion: Use the AT6005-4AC’s flexible and configurable I/O to implement bus bridges, protocol converters, or offload interface tasks from a host processor.
- Prototyping and Adaptive Hardware: Take advantage of in-system partial reconfiguration to iterate designs or adapt functionality in the field without full system downtime.
Unique Advantages
- Balanced Logic Density: 3,136 logic cells and ~15,000 usable gates provide a strong mix of capacity and granularity for complex custom functions without excessive device overhead.
- High-Speed Operation: System speeds > 100 MHz and flip-flop toggle rates > 250 MHz support demanding timing requirements for performance-critical designs.
- Flexible, Driven I/O: Independently configurable I/O with programmable thresholds, slew-rate control and combinable drive strength helps match signaling requirements and reduce external components.
- Field Reconfigurability: Complete and partial in-system reconfiguration preserves machine state and enables upgrades or feature changes in deployed systems.
- Predictable Timing: Low clock skew across the chip and defined input/output delays simplify timing closure and deterministic behavior in synchronous designs.
- Commercial Packaging and Compliance: Available in a 100-TQFP (14×14) surface-mount package with RoHS compliance for commercial electronics manufacturing.
Why Choose AT6005-4AC?
The AT6005-4AC pairs a register-rich, symmetrical cell architecture with high-speed timing and flexible I/O to deliver a programmable solution for commercial embedded and compute-accelerated applications. Its in-system reconfiguration and predictable timing make it suitable for designs that require field updates, hardware acceleration, or consolidation of discrete logic into a single programmable device.
Engineers selecting the AT6005-4AC gain a commercially graded FPGA in a compact 100-TQFP package backed by Microchip Technology’s AT6000 series architecture—providing a scalable platform for custom logic, interface solutions, and adaptive hardware implementations.
Request a quote or submit an inquiry for the AT6005-4AC to confirm availability, pricing, and lead time for your next design.

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