AT6003-2AC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 80 1600 100-TQFP |
|---|---|
| Quantity | 1,240 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 80 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 1600 | ||
| Number of Gates | 9000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6003-2AC – AT6000(LV) Field Programmable Gate Array (FPGA) IC, 80 I/O, 1600 Logic Elements, 100‑TQFP
The AT6003-2AC is an SRAM-based FPGA from Microchip Technology’s AT6000(LV) family, delivered in a 100‑pin TQFP (14×14) package. This device provides 1,600 logic elements, approximately 9,000 usable gates, and 80 user I/Os, making it suitable for reconfigurable coprocessors and compute‑intensive logic implementations.
Built around a symmetrical cell array and a flexible busing network, the AT6003-2AC supports in-system reconfiguration and deterministic I/O control, offering designers a balance of performance, configurability, and low-power operation for commercial embedded systems.
Key Features
- Core Architecture Symmetrical array of 1,600 logic elements (40 × 40 cell array) and up to 1,600 registers, optimized for cache logic and hardware acceleration.
- Logic Capacity Approximately 9,000 usable gates and up to 1,600 registers enable mid-range logic integration for compute‑intensive tasks.
- I/O Flexibility 80 user I/Os with independently configurable TTL/CMOS input thresholds, open-collector/tristate outputs, programmable slew-rate control, and 16 mA drive (combinable up to 64 mA).
- Performance System speeds greater than 100 MHz with flip‑flop toggle rates above 250 MHz; measured input delays of ~1.2 ns/1.5 ns and output delays of ~3.0 ns/6.0 ns support high-speed signaling.
- In‑System Reconfiguration Supports complete and partial in‑system reconfiguration without loss of data or machine state for adaptive hardware updates.
- Power Very low standby current (500 μA / 200 μA) and typical operating currents in the range of 25–45 mA for this device class, enabling power‑sensitive embedded designs.
- Supply & Temperature Designed for 5.0 V operation (VCC = 4.75 V to 5.25 V) and specified for commercial temperature range (0 °C to 70 °C).
- Package 100‑TQFP (14×14) surface-mount package for compact board-level integration; RoHS compliant.
Typical Applications
- Reconfigurable Coprocessors Use the device as a hardware accelerator to offload compute‑intensive tasks and adapt logic functions in‑field through in‑system reconfiguration.
- High‑Speed Logic Implement timing‑sensitive state machines and data paths that benefit from >100 MHz system speeds and fast flip‑flop toggle rates.
- Peripheral & Interface Glue Custom protocol bridging, bus interfacing, and I/O aggregation using the device’s independently configurable inputs and outputs.
- Adaptive Hardware Functions Deploy cache logic and reusable hard macro functions to create adaptive, application‑specific hardware blocks.
Unique Advantages
- In‑System Reconfiguration: Complete or partial reconfiguration without losing data or machine state enables firmware‑style updates to hardware behavior.
- Deterministic I/O Control: Programmable thresholds, slew‑rate control and combinable drive strengths simplify interfacing with a wide range of peripherals.
- Compact, Tested Package: 100‑TQFP (14×14) surface‑mount package provides compact integration and is 100% factory‑tested for reliability in commercial applications.
- Balanced Power Profile: Low standby current and modest operating current ranges help reduce system power consumption in always‑on or battery‑assisted designs.
- Series‑Level Performance: Features drawn from the AT6000(LV) series—such as >100 MHz system speeds and <1 ns column clock skew—enable consistent performance expectations across family migrations.
Why Choose AT6003-2AC?
The AT6003-2AC offers a practical mix of logic density, configurable I/O and reconfiguration capabilities for mid‑range FPGA requirements in commercial embedded systems. Its symmetrical cell array architecture and busing network deliver predictable routing and performance for compute‑intensive applications.
Designed for customers seeking reconfigurable hardware with manageable power consumption and compact board footprint, the AT6003-2AC provides a scalable option within the AT6000(LV) family backed by Microchip Technology’s FPGA toolchain and factory testing.
If you would like pricing, availability, or a formal quote for the AT6003-2AC, submit a request for a quote or contact the supplier’s sales channel to start the procurement process.

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