LCMXO640E-5B256C
| Part Description |
MachXO Field Programmable Gate Array (FPGA) IC 159 640 256-LFBGA, CSPBGA |
|---|---|
| Quantity | 1,053 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 256-CABGA (14x14) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 256-LFBGA, CSPBGA | Number of I/O | 159 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 80 | Number of Logic Elements/Cells | 640 | ||
| Number of Gates | N/A | ECCN | EAR99 | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of LCMXO640E-5B256C – MachXO Field Programmable Gate Array (FPGA) IC 159 640 256-LFBGA, CSPBGA
The LCMXO640E-5B256C is a MachXO family FPGA optimized for glue logic, bus bridging, bus interfacing, power-up control and general control logic. It combines non-volatile configuration and FPGA-style LUT-based logic in a single, instant-on device with a compact 256-ball BGA package for space-constrained designs.
With 640 logic elements, up to 159 I/O and support for in-field reconfiguration and low-power modes, this commercial-grade device targets applications that need fast startup, flexible I/O and a high pin-to-logic density in a surface-mount package.
Key Features
- Core Logic 640 logic elements implemented across 80 configurable logic blocks (CLBs) for flexible combinational and sequential logic implementation.
- Non-volatile, Instant-on Configuration MachXO family architecture provides single-chip, non-volatile configuration with instant-on startup and in-field reconfiguration capabilities (background programming via JTAG).
- Memory Approximate 6.1 Kbits of distributed RAM available for small data buffering and LUT-based storage; no embedded block SRAM blocks on this device variant.
- I/O and Interface Flexibility Up to 159 I/Os in the 256-ball package, enabling high pin-to-logic connectivity for bus interfacing and signal routing.
- Power and Low-Power Modes Core voltage specified at 1.14 V to 1.26 V. Family-level features include a Sleep Mode that can achieve significant static current reduction.
- Package and Mounting 256-ball LFBGA / caBGA (14 × 14 mm) surface-mount package, RoHS compliant for modern assembly processes.
- Commercial Temperature Grade Rated for operation from 0 °C to 85 °C, suitable for commercial and many industrial-adjacent applications that do not require extended temperature ranges.
- System-Level Support MachXO family supports JTAG programming and in-system programming; designs for this family are supported by ispLEVER design tools as noted in the MachXO data sheet.
Typical Applications
- Glue Logic Implement board-level glue logic to replace discrete gate arrays and simplify PCB routing.
- Bus Bridging and Interfacing Provide flexible I/O mapping and protocol adaptation between subsystems with high pin density.
- Power-up and Control Sequencing Manage system power sequencing and supervisory control with instant-on behavior and on-chip configuration.
- General Control Logic Implement state machines, control paths and peripheral interfaces where single-chip non-volatile configuration and reconfigurability are advantageous.
Unique Advantages
- Single-chip non-volatile FPGA: Combines FPGA-style LUT logic with on-chip non-volatile configuration for instant-on systems without external configuration memory.
- High pin-to-logic density: 159 I/Os paired with 640 logic elements enable compact designs that require substantial I/O connectivity relative to logic capacity.
- In-field update capability: Supports background programming and JTAG-based reconfiguration for maintenance and feature updates without full system downtime.
- Low-power options: Sleep Mode from the MachXO family provides substantial static current reduction for power-sensitive applications.
- Compact BGA packaging: 256-ball 14 × 14 mm package supports surface-mount assembly and space-optimized board layouts.
- Design tool support: Family-level support by ispLEVER tools aids synthesis, place-and-route and timing verification workflows.
Why Choose LCMXO640E-5B256C?
The LCMXO640E-5B256C positions itself as a compact, commercial-grade non-volatile FPGA for designs that require instant-on behavior, flexible I/O and modest logic capacity. Its combination of 640 logic elements, approximately 6.1 Kbits of distributed RAM and 159 I/Os in a 256-ball BGA package makes it a practical choice for board-level control, interface bridging and power sequencing tasks.
Supported by MachXO family design methodology and ispLEVER tooling, this device is suitable for engineering teams seeking a single-chip solution to reduce BOM complexity, enable in-field updates, and accelerate system startup behavior while meeting standard commercial temperature and RoHS requirements.
Request a quote or submit an inquiry to obtain pricing and availability for the LCMXO640E-5B256C.

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