EN25QA128A-104HIP(2T)
| Part Description |
128 M-bit SPI NOR Flash (Industrial) |
|---|---|
| Quantity | 1,763 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 8-pin SOP 200mil | Memory Format | NOR Flash | Technology | SPI NOR Flash | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 128 Mbit | Access Time | 7 ns | Grade | Industrial | ||
| Clock Frequency | 104 MHz | Voltage | 2.5V | Memory Type | Non-Volatile | ||
| Operating Temperature | -40°C – 85°C | Write Cycle Time Word Page | 3 ms | Packaging | 8-pin SOP 200mil | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 1M x 8 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | N/A | ECCN | EAR99 | HTS Code | 8542.32.00.71 |
Overview of EN25QA128A-104HIP(2T) – 128 M-bit SPI NOR Flash (Industrial)
The EN25QA128A-104HIP(2T) is a serial NOR Flash memory device designed for industrial embedded systems requiring non-volatile code and data storage. Built on an SPI serial interface architecture, the device supports Standard, Dual and Quad SPI read modes and high-speed operation to accommodate firmware storage, code patching and secure data segments.
Key value comes from high read throughput (up to 104 MHz), fine-grained sector management and robust program/erase protection mechanisms, all supplied in an industry-temperature, surface-mount SOP package for compact system designs.
Key Features
- Memory Core 128 M-bit serial NOR Flash organized to support page-programming (256 bytes per programmable page) and multiple erase granularities.
- Serial SPI Interface Standard, Dual and Quad SPI supported with Standard/Dual Quad read modes; SPI clock up to 104 MHz (Standard/Dual) and quad rates supported with configurable dummy cycles.
- Sector and Block Architecture Uniform sector architecture with 4 Kbyte sectors and larger 32 Kbyte / 64 Kbyte block options; individual sector or block erase and full chip erase supported.
- Program / Erase Performance Typical page program time ~0.5 ms; typical sector erase ~40 ms, half-block ~200 ms, block ~300 ms and full chip erase ~60 s (typical values).
- Write Protection & Security Software and hardware write protection options, permanent protection bits and a lockable 512-byte OTP security sector plus a readable unique ID.
- Low Power Typical active current ~5 mA and typical power-down current ~1 μA for low standby power consumption.
- Reliability Minimum 100K program/erase cycles per sector and 20-year data retention (typical).
- Package & Temperature Supplied in an 8-pin SOP 200mil surface-mount package and rated for industrial operating temperatures from −40°C to 85°C.
Typical Applications
- Firmware Storage and Boot Code Store application firmware and bootloaders with support for in-field updates and page-level programming.
- Field Upgrades & Code Patching Fine-grained sector protection and individual sector erase allow reliable code patching without exposing other areas of memory.
- Industrial Embedded Systems Industrial temperature rating and compact SOP packaging make the device suitable for controllers, sensors and automation modules.
- Secure Data Segments Lockable 512-byte OTP and hardware/software protection features support secure storage of device configuration or unique IDs.
Unique Advantages
- High-throughput SPI interface: Up to 104 MHz SPI operation and Quad Output capability enable fast code and data reads to minimize system boot and update times.
- Granular erase and protection: 4 Kbyte uniform sectors and multiple block sizes let designers update small regions of memory while keeping other regions protected.
- Field-proven program/erase performance: Typical page program and sector/block erase times provide predictable update behavior for maintenance and firmware management.
- Low standby power: Sub-microamp power-down current helps reduce system power consumption in low-activity states.
- Industrial-grade operation: −40°C to 85°C operating range and surface-mount SOP packaging support rugged embedded deployments.
- Long-term data integrity: Designed for a minimum of 100K program/erase cycles and typical 20-year data retention to support long-lived products.
Why Choose EN25QA128A-104HIP(2T)?
The EN25QA128A-104HIP(2T) combines high-speed SPI read performance with robust protection and erase granularity in an industrial-temperature, surface-mount package. It is well suited for designs that require reliable firmware storage, secure data segments and predictable program/erase behavior for field updates.
This device targets engineers building industrial and embedded systems who need a compact, low-power serial NOR Flash solution with clear endurance and retention characteristics, built-in protection options and support for Standard/Dual/Quad SPI interfaces.
Request a quote or submit an inquiry to receive pricing, availability and technical support for EN25QA128A-104HIP(2T).
Date Founded: 1998
Headquarters: Hsinchu Science Park, Hsinchu, Taiwan
Employees: 400+
Revenue: $377.8 Million
Certifications and Memberships: N/A