EN25QA64A-104HIP
| Part Description |
64 Megabit SPI NOR Flash (Industrial) |
|---|---|
| Quantity | 1,731 Available (as of May 6, 2026) |
Specifications & Environmental
| Device Package | 8-pin SOP 200mil | Memory Format | NOR Flash | Technology | SPI NOR Flash | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 64 Mbit | Access Time | 7 ns | Grade | Industrial | ||
| Clock Frequency | 104 MHz | Voltage | 2.5V | Memory Type | Non-Volatile | ||
| Operating Temperature | -40°C – 85°C | Write Cycle Time Word Page | 3 ms | Packaging | 8-pin SOP 200mil | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 8M x 8 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | N/A | ECCN | EAR99 | HTS Code | 8542.32.00.71 |
Overview of EN25QA64A-104HIP – 64 Megabit SPI NOR Flash (Industrial)
The EN25QA64A-104HIP is a 64 Megabit serial NOR Flash memory device from ESMT designed for industrial embedded systems. It implements a Serial Peripheral Interface (SPI) architecture with Standard, Dual and Quad SPI modes to deliver high-throughput, non-volatile code and data storage.
Built for systems that require field updates, selective block protection and long-term data retention, the device combines high-speed read performance with sector-level erase flexibility and industrial temperature operation.
Key Features
- Memory Capacity & Organization — 64 M-bit density with an 8M × 8 organization providing 8,192 Kbytes and 32,768 programmable pages (256 bytes per page).
- SPI Interface & Modes — Standard, Dual and Quad SPI support with Standard SPI signals (CLK, CS#, DI, DO) and Dual/Quad DQ lines for higher throughput.
- High Read Performance — Fast read options up to 104 MHz in Standard and Dual SPI (104 MHz with 1 dummy byte); Quad SPI supports 104 MHz with 3 dummy bytes. Normal read at 83 MHz.
- Program & Erase Performance — Typical page program time 0.5 ms; typical sector erase 40 ms; half-block and block erase times typically 200 ms and 300 ms respectively; typical chip erase 32 seconds.
- Uniform Sector Architecture — 4-Kbyte uniform sectors (2,048 sectors), 256 blocks of 32-Kbyte and 128 blocks of 64-Kbyte enabling per-sector or per-block erase.
- Protection & Security — Software and permanent protection options, lockable 512-byte OTP security sector, volatile status register bits, and Read Unique ID Number support for device identification.
- Reliability — Minimum 100K program/erase cycles per sector and typical data retention of 20 years.
- Low Power — Typical active current ~5 mA and typical power-down current ~1 μA for energy-conscious designs.
- Voltage & Temperature — Single supply operation with full voltage range 2.7–3.6 V and industrial operating temperature range −40 °C to 85 °C.
- Package Options — Available in 8‑lead SOP (200 mil) and 24‑ball TFBGA (6 × 8 mm) Pb‑free packages.
Typical Applications
- Firmware Storage and Field Updates — Store application code and enable in-field firmware patches or module updates using page program and sector/block erase operations.
- Code Patching / Modular Software Updates — Protect critical regions while selectively unprotecting blocks for targeted code or module modifications.
- Industrial Control & Configuration Storage — Retain configuration, calibration, and parameter sets with long data-retention and high endurance in industrial environments.
- Device Identification & Security — Use the Read Unique ID and lockable 512‑byte OTP sector for device identity and secure small data storage.
Unique Advantages
- Flexible SPI Performance: Standard, Dual and Quad SPI support with up to 104 MHz operation enables scalable read throughput to match system requirements.
- Uniform Sectors for Simplified Updates: 4-Kbyte uniform sectors and multiple block sizes allow precise erase/program operations without affecting adjacent code or data.
- Fast Program and Erase: Typical page program of 0.5 ms and sector erase of 40 ms help minimize downtime during firmware updates and manufacturing programming.
- Industrial-Grade Reliability: Minimum 100K program/erase cycles and 20-year data retention provide predictable long-term behavior for deployed systems.
- Low-Power Standby: Very low power‑down current (~1 μA) supports energy-sensitive designs while active current remains modest (~5 mA).
- Hardware-Level Security Options: Permanent and software block protection plus an OTP sector support secure storage and controlled updates.
Why Choose EN25QA64A-104HIP?
The EN25QA64A-104HIP balances high-speed SPI reads with practical programming and erase performance in a compact, industrial-grade package. Its support for Standard/Dual/Quad SPI modes, uniform sector architecture, and robust protection features make it well suited to embedded systems that require reliable non-volatile code and data storage with field update capability.
Engineers designing industrial equipment, programmable controllers, or devices requiring secure identification and long-term retention will find the EN25QA64A-104HIP provides the endurance and flexibility needed for sustained deployments while simplifying selective updates and protection strategies.
Request a quote or submit an inquiry for pricing, availability, and packaging options to evaluate the EN25QA64A-104HIP for your next design.
Date Founded: 1998
Headquarters: Hsinchu Science Park, Hsinchu, Taiwan
Employees: 400+
Revenue: $377.8 Million
Certifications and Memberships: N/A