SC82360SLAHC1
| Part Description |
Intel 82360SL Peripheral I/O Subsystem for Intel386 SL |
|---|---|
| Quantity | 1,180 Available (as of October 8, 2026) |
| Product Category | Microprocessors |
|---|---|
| Part Series | Intel386 SL |
| Manufacturer | Intel |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 1 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 208-PQFP | ECCN | EAR99 | Grade | Commercial | ||
|---|---|---|---|---|---|---|---|
| Graphics Acceleration | No | HTS Code | 8542.39.0001 | Moisture Sensitivity Level | 3 (168 Hours) | ||
| Mounting Method | Surface Mount | Package / Case | 208-BQFP | RAM Controllers | DRAM | ||
| REACH Compliance | REACH Unaffected | RoHS Compliance | RoHS non-compliant | Voltage – I/O | 5 V |
Overview of SC82360SLAHC1 - Intel 82360SL Peripheral I/O Subsystem for Intel386 SL
The SC82360SLAHC1 is Intel's 82360SL Peripheral I/O Subsystem, one of the two chips in the Intel386 SL Microprocessor SuperSet. It gathers the standard PC/AT peripheral set and a wide range of CPU and memory support logic onto a single device, pairing with the Intel386 SL CPU to form a complete, power-managed mobile platform. Built in Intel's one-micron CHMOS-IV technology with a fully static design, it was engineered for the battery-powered 386SL notebooks and embedded systems of its era.
Key Features
- Integrated DMA and interrupts - two 8237-compatible DMA controllers providing eight channels, plus two 8259A-compatible programmable interrupt controllers.
- Timers and real-time clock - two 8254-compatible interval timer/counters and a 146818-compatible real-time clock with a 256-byte low-power RAM block.
- Serial and parallel I/O - two 16450-compatible UART serial channels and a parallel printer port, with address decoding for multiple COM and LPT devices.
- Memory and refresh support - a dedicated low-power DRAM refresh timer that keeps main memory alive while the CPU is idle.
- Power management - an extensive set of power-management facilities suited to battery-operated designs.
- ISA backplane and peripherals - an ISA-compatible system bus plus interfaces for external floppy, IDE hard disk, and keyboard controllers.
- On-chip clock generation - internal variable-frequency clock generators for the CPU, backplane, video subsystem, and an external math coprocessor.
Typical Applications
- 386SL notebook systems - the peripheral half of mobile Intel386 SL designs where power efficiency was critical.
- Embedded 386-class systems - industrial and instrumentation boards needing a full PC/AT peripheral set.
- Legacy system repair - sustaining and servicing deployed 386SL SuperSet platforms.
Unique Advantages
- Whole peripheral set in one chip - DMA, interrupt, timer, serial, parallel, and RTC functions that once filled several discrete controllers are integrated here, shrinking a 386 board dramatically.
- Static, power-managed design - the fully static CHMOS-IV implementation lets the clock be stopped, a key enabler for notebook battery life.
- PC/AT software compatibility - 8237, 8259A, 8254, 16450, and 146818 compatibility preserve the familiar PC programming model.
- Reduced component count - replacing a shelf of discrete controllers with one device cuts cost, power, and board area in a 386-class system.
Why Choose SC82360SLAHC1?
The SC82360SLAHC1 is the companion peripheral subsystem that completes an Intel386 SL design, and it remains relevant mainly for maintaining the mobile and embedded 386SL systems still in the field. Its deep integration of the classic PC/AT controllers, low-power DRAM refresh, and power management made compact, battery-friendly 386 platforms possible, and it keeps those platforms serviceable today. Because it carries the dual 8237, 8259A, and 8254 blocks plus 16450 serial and a 146818 RTC, a single replacement part restores most of a 386SL board's I/O at once.
Contact us for pricing, availability, and lead time on the SC82360SLAHC1, and let us know your system so we can confirm the correct variant.

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