AT40K20-2AJC
| Part Description |
AT40K/KLV Field Programmable Gate Array (FPGA) IC 62 8192 1024 84-LCC (J-Lead) |
|---|---|
| Quantity | 619 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 84-PLCC (29.31x29.31) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 84-LCC (J-Lead) | Number of I/O | 62 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 2 (1 Year) | Number of LABs/CLBs | 1024 | Number of Logic Elements/Cells | 1024 | ||
| Number of Gates | 30000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 8192 |
Overview of AT40K20-2AJC – Field Programmable Gate Array, 5 V, 84‑LCC (J‑Lead)
The AT40K20-2AJC is an SRAM-based FPGA from the AT40K family designed for high-performance, reconfigurable logic tasks. It provides 1,024 logic elements, approximately 8,192 bits of distributed on-chip RAM, and up to 62 I/O pins in an 84‑pin PLCC (J‑lead) surface-mount package.
Built for applications that require fast arithmetic and flexible memory, this device supports family-level features such as Cache Logic dynamic reconfigurability, fast array multipliers, and multi-clock distribution to accelerate DSP, video and system-control functions.
Key Features
- Core Performance – Family-level system speeds up to 100 MHz and array multipliers greater than 50 MHz; internal tri-state capability in each cell enables flexible datapath design.
- Logic Capacity – 1,024 logic elements (cells) providing approximately 30,000 usable gates for medium-complexity designs.
- Embedded Memory (FreeRAM) – Approximately 8,192 bits of distributed 10 ns SRAM on-chip; supports single- or dual-port, synchronous or asynchronous RAM configurations for FIFOs and scratch-pad memory.
- I/O and Clocking – 62 user I/Os on this package; family architecture supports up to eight global clocks and additional PCI clock options for low-skew clock distribution and flexible timing control.
- Reconfiguration – Cache Logic dynamic partial/full in-system reconfigurability (family feature) enabling adaptive updates without losing stored data.
- Package & Mounting – 84‑LCC (J‑Lead) / 84‑PLCC supplier package (29.31 × 29.31 mm), surface-mount mounting for PCB assembly.
- Power & Temperature – 5 V supply range (4.75 V to 5.25 V) and commercial operating temperature 0 °C to 70 °C.
- Standards & Tools – Family supports industry-standard design tool integration and automatic component generators (as documented for the AT40K series).
Typical Applications
- Signal Processing Coprocessors – Implement array multipliers and arithmetic-heavy functions for DSP acceleration alongside a host processor.
- Video and Image Processing – Use the device’s fast multipliers and embedded RAM for filtering, transforms and coefficient storage in compression/decompression pipelines.
- Interface and Glue Logic – Provide flexible I/O and reconfigurable logic to implement protocol bridging, bus interfacing and custom peripheral control.
- Encryption and Secure Data Paths – Implement arithmetic and bit-manipulation cores for encryption, hashing and related crypto functions using on-chip logic and RAM.
Unique Advantages
- Fast, Deterministic Memory Access: Distributed 10 ns SRAM enables low-latency local storage without consuming logic resources, simplifying FIFO and buffer designs.
- Dynamic Reconfigurability: Cache Logic capability supports partial or full in-system reconfiguration to update algorithms or coefficients without full device downtime.
- Balanced I/O and Logic: 62 I/Os and 1,024 logic elements provide a compact, versatile platform for mid-range designs that need both logic density and peripheral connectivity.
- Proven FPGA Tool Integration: Series-level integration with common synthesis and simulation toolflows accelerates development and enables timing-driven design.
- Surface-Mount, Standard Package: 84‑PLCC (J‑lead) packaging supports established board assembly processes and straightforward mechanical integration.
Why Choose AT40K20-2AJC?
The AT40K20-2AJC combines a compact logic array, fast on-chip SRAM, and family-proven features such as Cache Logic reconfigurability and multi-clock distribution to address mid-range FPGA requirements. It is suited for designers who need deterministic memory access, flexible reconfiguration, and DSP-oriented arithmetic capabilities in a commercial-temperature, 5 V solution.
This device is appropriate for system designers implementing coprocessor functions, video or signal-processing pipelines, protocol interfaces, and other embedded applications where balanced logic density, embedded RAM and flexible I/O are required. The AT40K family’s tool and IP support help maintain scalability and reduce integration time.
Request a quote or submit a purchase inquiry for the AT40K20-2AJC to receive pricing and availability information tailored to your project requirements.

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