AT40K20-2AQC
| Part Description |
AT40K/KLV Field Programmable Gate Array (FPGA) IC 78 8192 1024 100-TQFP |
|---|---|
| Quantity | 1,260 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 78 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1024 | Number of Logic Elements/Cells | 1024 | ||
| Number of Gates | 30000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 8192 |
Overview of AT40K20-2AQC – AT40K/KLV Field Programmable Gate Array, 100‑TQFP
The AT40K20-2AQC from Microchip Technology is an SRAM-based field programmable gate array (FPGA) in a 100‑TQFP (14×14) package. It provides 1,024 logic elements, approximately 8,192 bits of embedded memory, and 78 user I/Os for mid-density, reconfigurable logic implementations.
Designed for applications that require on-board reconfigurability and DSP-style processing, this device combines fast distributed SRAM, array multiplier capability, and support for dynamic reconfiguration to accelerate tasks such as filters, transforms, and other computation-intensive functions.
Key Features
- Core Performance – Series-level system speeds to 100 MHz and array multipliers operating above 50 MHz enable high-throughput logic and arithmetic operations.
- Logic Capacity – 1,024 logic elements (cells) and approximately 30,000 gates provide a mid-range fabric suitable for coprocessor and accelerator roles.
- Embedded Memory (FreeRAM) – Approximately 8,192 bits of distributed 10 ns SRAM that can be configured as single- or dual-port, synchronous or asynchronous memory for FIFOs, scratch pads, and coefficient storage without consuming separate logic resources.
- I/O and Packaging – 78 I/O pins in a 100‑TQFP (14×14) surface-mount package for compact board integration and signal routing.
- Reconfigurability – Cache Logic dynamic partial/full in-system reconfigurability and unlimited re-programmability via serial or parallel modes enable adaptive designs and field updates.
- Clocking and Control – Series-level support for multiple global clocks, including fast, low-skew distribution and programmable edge behavior to manage synchronous domains and low-power shutdown of distributed clocks.
- Electrical and Environmental – 5 V supply recommended (operating range 4.75 V to 5.25 V) and commercial operating range of 0 °C to 70 °C. RoHS compliant.
- Design Ecosystem – Series documentation highlights support for industry-standard synthesis and CAD tool integration to streamline development and migration within the family.
Typical Applications
- DSP Coprocessors – Implement FIR filters, FFTs, convolvers and other arithmetic-intensive blocks to offload host processors and accelerate signal processing pipelines.
- Video and Multimedia Processing – Useful for video compression/decompression and transform operations where on-chip multipliers and fast embedded SRAM improve throughput.
- Adaptive and Reconfigurable Systems – In-system partial or full reconfiguration enables fast design updates and adaptive coefficient replacement for evolving algorithms.
- Encryption and Data Processing – Implement custom encryption engines, streaming transforms and protocol accelerators using the device’s logic and memory resources.
Unique Advantages
- Balanced Logic and Memory – 1,024 logic elements paired with ~8 Kbits of embedded SRAM supports medium-complexity designs without external memory.
- High-Speed Arithmetic – Array multiplier capability and fast SRAM (10 ns) enable high-speed arithmetic and DSP functions on-chip.
- In-System Reconfiguration – Cache Logic reconfigurability allows partial or full updates without loss of data, speeding iterative development and field upgrades.
- Compact, Surface-Mount Package – 100‑TQFP (14×14) package supports dense PCB layouts while providing a generous set of I/Os for peripheral interfacing.
- Commercial Temperature and 5 V Operation – Designed for standard commercial environments with a 4.75–5.25 V supply range and 0 °C to 70 °C operating range.
- RoHS Compliant – Conforms to RoHS requirements for environmentally conscious designs.
Why Choose AT40K20-2AQC?
The AT40K20-2AQC positions itself as a versatile mid-density FPGA for applications that need configurable logic, embedded SRAM, and on-chip arithmetic acceleration within a compact 100‑TQFP package. Its combination of 1,024 logic elements, approximately 8,192 bits of distributed SRAM, and dynamic reconfiguration capabilities makes it suitable for designers implementing DSP coprocessors, multimedia processing blocks, and adaptive systems.
Backed by a family-level ecosystem that supports industry-standard design flows and pin-compatible package options across the series, the AT40K20-2AQC provides a practical balance of performance, reconfigurability, and board-level integration for commercial embedded designs.
Request a quote or submit a product inquiry to evaluate the AT40K20-2AQC for your next design and get pricing and availability details.

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