AT6002-2AC

The AT6002-2AC is an AT6000(LV) Series SRAM-based Field Programmable Gate Array (FPGA) featuring approximately 6,000 usable gates and 1,024 logic elements in a 100‑TQFP (14×14) surface-mount package. The device is designed for reconfigurable coprocessor and compute-intensive logic implementations that benefit from the AT6000 Series architecture.

Built around a symmetrical array of small, efficient logic cells and a flexible busing network, the device supports in-system reconfiguration and a range of programmable I/O and clocking options. Key device-level specifications include 80 I/O pins, a 5.0 V supply range (4.75 V to 5.25 V), and commercial operating temperature from 0 °C to 70 °C. The device is RoHS compliant.

Key Features

• Core Architecture Symmetrical array of 1,024 logic elements with a flexible local and express busing network for efficient medium- and long-distance communication between cells.
• Logic Capacity Approximately 6,000 usable gates and up to 1,024 registers (device-level values from the AT6000 Series device table).
• High‑Performance Timing Series-level timing features include system speeds greater than 100 MHz and flip-flop toggle rates above 250 MHz; input delays of ~1.2 ns/1.5 ns and output delays of ~3.0 ns/6.0 ns are documented at the series level.
• I/O Flexibility 80 device I/O pins with independently configurable I/O (TTL/CMOS thresholds), open-collector/tristate outputs, programmable slew-rate control, and I/O drive of 16 mA (combinable to 64 mA) as described for the series.
• In-System Reconfiguration Supports complete or partial in-system reconfiguration without loss of data or machine state, enabling adaptive hardware updates and runtime changes.
• Low-Power Options Series-level power figures include standby currents of 500 µA/200 µA and typical operating currents reported across devices; the AT6002 device typically falls in the lower operating-current range noted in the series documentation.
• Programmable Clocking Independently controlled column clocks and resets with clock skew of less than 1 ns across the chip, providing deterministic timing control for column-based logic.
• Package and Environmental Surface-mount 100‑TQFP (14×14) package, commercial grade with an operating temperature range of 0 °C to 70 °C, and RoHS compliance.
• Development Support The AT6000 Series is supported by Atmel PC- and workstation-based Integrated Development System tools with multiple design entry methods, as documented in the series materials.

Typical Applications

• Reconfigurable Coprocessors Implement hardware-accelerated functions and offload compute-intensive logic using the device's reconfigurable array and in-system reconfiguration capability.
• Cache Logic and Adaptive Hardware Implement cache-logic style designs and adaptive hardware that benefit from the series architecture of small, efficient cells and flexible busing.
• High-Speed Control and Interface Logic Use programmable I/O, independent column clocks, and low input/output delays to implement deterministic control, interface bridging, and timing-sensitive peripheral logic.

Unique Advantages

• Symmetrical, Efficient Array: The 1,024-element array and sector-based busing architecture deliver predictable routing and compact logic implementation for compute-focused designs.
• In-System Reconfiguration: Complete or partial configuration changes can be made without loss of data or machine state, simplifying iterative development and field updates.
• Flexible I/O and Clocking: Independently configurable I/O thresholds, programmable slew-rate and drive, plus independently controlled column clocks and resets provide design flexibility for mixed-signal and timing-critical interfaces.
• Low-Power Operation: Series-level standby and typical operating currents enable energy-conscious designs; the AT6002 device sits in the lower operating-current range documented for the series.
• Compact, Surface-Mount Package: 100‑TQFP (14×14) surface-mount package supports dense board-level integration while remaining RoHS compliant.
• Toolchain Availability: Series support includes Atmel integrated development tools and multiple design entry methods to streamline design entry, synthesis and configuration.

Why Choose AT6002-2AC?

The AT6002-2AC combines a compact, efficient logic array with the AT6000 Series' flexible busing and reconfiguration capabilities to address compute-intensive and adaptive hardware tasks in commercial-temperature applications. With approximately 6,000 usable gates, 1,024 logic elements, 80 I/Os, and programmable clocking and I/O options, the device is well suited for designers needing in-field reconfigurability and deterministic timing control.

Packaged in a 100‑TQFP surface-mount package and compliant with RoHS, the AT6002-2AC is appropriate for commercial electronic products where low standby current, configurable I/O, and development-tool support are required.

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