AT6005ALV-4AC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 108 3136 144-LQFP |
|---|---|
| Quantity | 1,388 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 144-LQFP (20x20) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 144-LQFP | Number of I/O | 108 | Voltage | 3.135 V - 3.465 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 3136 | ||
| Number of Gates | 15000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6005ALV-4AC – AT6000(LV) Field Programmable Gate Array (FPGA) IC 108 3136 144-LQFP
The AT6005ALV-4AC is an SRAM-based Field Programmable Gate Array (FPGA) from the AT6000(LV) series, offered in a 144-LQFP (20×20) surface-mount package. It provides 3,136 logic cells (equivalent to 15,000 usable gates) and 108 user I/Os, delivering a compact reconfigurable logic device for compute‑intensive and adaptive hardware tasks.
Designed for high-speed logic implementation, the device supports system speeds greater than 100 MHz and flip‑flop toggle rates above 250 MHz. It operates from a 3.135 V to 3.465 V supply and is specified for commercial temperature operation from 0 °C to 70 °C. The device is RoHS compliant.
Key Features
- Core architecture Symmetrical array of 3,136 cells (56 × 56 rows × columns) implementing 15,000 usable gates and up to 3,136 registers for on-chip state and buffering.
- High-performance timing System speeds > 100 MHz, flip‑flop toggle rates > 250 MHz, input delays of 1.2 ns / 1.5 ns and output delays of 3.0 ns / 6.0 ns for deterministic timing behavior.
- Flexible clocking and reset Independently controlled column clocks and column resets with clock skew less than 1 ns across the chip for synchronized, low-skew designs.
- Configurable I/O 108 user I/Os with TTL/CMOS input thresholds, open-collector/tristate outputs, programmable slew-rate control and base I/O drive of 16 mA (combinable up to 64 mA).
- Low-power operation Typical operating currents for the AT6005 family are specified (40–80 mA for AT6005) with very low standby currents reported at the series level, enabling energy-efficient designs.
- Package and mounting 144-LQFP (20 × 20) surface-mount package suitable for compact board-level integration; commercial grade operating temperature of 0 °C to 70 °C.
- Development support Series supports PC- and workstation-based integrated development tools for design entry and implementation (Atmel Integrated Development System referenced in series documentation).
Typical Applications
- Reconfigurable coprocessors Implement hardware-accelerated functions and offload compute-intensive tasks using the device’s dense logic cell array and high-performance timing.
- Adaptive hardware and cache logic Deploy adaptive or cache-style logic that can be reconfigured in-system to respond to changing algorithmic needs without losing machine state.
- High-speed I/O interfacing Use programmable I/O thresholds, drive strengths and slew-rate control to interface with a variety of TTL/CMOS peripherals and custom I/O functions.
- Custom logic and state machines Build complex state machines and custom hard-macro functions using the provided registers and reusable component generators supported by the series tools.
Unique Advantages
- Deterministic, low-skew clocking: Independently controlled column clocks and resets with < 1 ns skew enable tight timing across the array for synchronized, high-performance designs.
- High logic density in a compact package: 3,136 cells and 15,000 usable gates in a 144-LQFP provide a balance of functionality and board-space efficiency.
- Programmable, robust I/O: TTL/CMOS thresholds, open-collector/tristate options and adjustable drive/slew control simplify interfacing and reduce external component counts.
- Fast signal paths: Measured input/output delays and high toggle rates support designs that require rapid combinational and sequential response.
- Commercial-grade readiness: Operates over a 0 °C to 70 °C range with specified supply window of 3.135 V to 3.465 V, suitable for general embedded and electronics applications.
Why Choose AT6005ALV-4AC?
The AT6005ALV-4AC combines a high-density cell array, fast timing characteristics and flexible I/O control in a compact 144-LQFP package. Its architecture and series development tools make it suitable for designers implementing reconfigurable coprocessing, adaptive logic and custom acceleration functions where predictable timing and flexible interfacing are required.
With series-level tool support and consistent pin locations across the AT6000 family, the device offers design portability and straightforward migration within the series. The AT6005ALV-4AC is a practical choice for engineering teams seeking a commercially graded FPGA with clear electrical and timing specifications.
Request a quote or submit an inquiry to obtain pricing, lead-time and availability for the AT6005ALV-4AC.

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