AT6010H-2QC
| Part Description |
AT6000(LV) Field Programmable Gate Array (FPGA) IC 204 6400 240-BFQFP |
|---|---|
| Quantity | 1,508 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 240-PQFP (32x32) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 240-BFQFP | Number of I/O | 204 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | N/A | Number of Logic Elements/Cells | 6400 | ||
| Number of Gates | 30000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A |
Overview of AT6010H-2QC – AT6000(LV) Field Programmable Gate Array (FPGA) IC, 204 I/O, 6,400 Logic Elements, 240-BFQFP
The AT6010H-2QC is an AT6000(LV) series SRAM-based Field Programmable Gate Array (FPGA) supplied in a 240-BFQFP surface-mount package. Its symmetrical cell array and flexible busing network are designed for reconfigurable coprocessors and compute-intensive logic, delivering system-level performance and adaptive hardware capabilities.
This device targets applications that require high-speed logic, dense I/O, and on-board configurability, offering a balance of performance and low-power operation with proven architecture and a commercial-grade temperature range.
Key Features
- Core Performance System speeds greater than 100 MHz with flip-flop toggle rates exceeding 250 MHz; input delays ~1.2 ns/1.5 ns and output delays ~3.0 ns/6.0 ns as characterized in the AT6000(LV) series.
- Logic Resources Approximately 6,400 logic elements (cells) and up to 6,400 registers to implement compute-intensive functions and custom hardware acceleration.
- I/O and Interface Flexibility Up to 204 user I/Os with independently configurable thresholds (TTL/CMOS), open-collector/tristate outputs, programmable slew-rate control and I/O drive of 16 mA (combinable to 64 mA).
- Clocking and Synchronization Independently controlled column clocks and column resets with clock skew less than 1 ns across the chip for tight timing control across the array.
- Power and Voltage Supports 5.0 V operation (VCC = 4.75 V to 5.25 V). Typical operating current across the series ranges from 15 to 170 mA, with standby currents as low as 200 μA–500 μA depending on configuration.
- Architecture & Design Symmetrical grid of small cells connected by a local and express busing network, designed to support adaptive hardware, cache-logic implementations and efficient medium-/long-distance communication on-chip.
- Package & Mounting 240-BFQFP (240-PQFP, 32 × 32) surface-mount package suitable for compact board layouts; commercial-grade operating temperature 0 °C to 70 °C.
- Compliance RoHS compliant for regulatory and supply-chain consistency.
Typical Applications
- Reconfigurable Coprocessors Implement hardware-accelerated functions and offload compute-intensive tasks from the host processor using the device’s cell array and cache-logic design.
- High-speed Control and Signal Processing Use the device’s >100 MHz system speed and low I/O delays for timing-sensitive control loops and real-time signal paths.
- Adaptive Hardware and Prototyping Take advantage of complete/partial in-system reconfiguration to update logic without losing machine state, enabling iterative development and field updates.
- Dense I/O Interfaces Leverage up to 204 user I/Os with programmable thresholds and drive capability for mixed-signal and digital interface integration.
Unique Advantages
- High logic density in a compact package: 6,400 cells and up to 6,400 registers provide significant on-chip logic capacity in a 240-pin BFQFP footprint, simplifying board integration.
- Flexible, low-skew clocking: Independently controlled column clocks and resets with <1 ns skew enable synchronized, high-performance datapaths across the array.
- Programmable, robust I/O: Configurable input thresholds, output modes and combinable drive strength help reduce external buffer count and simplify system design.
- Reconfiguration without state loss: Support for complete/partial in-system reconfiguration enables adaptive hardware and field updates while preserving machine state.
- Power-scalable operation: Characterized operating currents from low tens of milliamps to higher-performance regions and low standby currents allow designers to balance performance and power.
- Commercial-grade reliability and compliance: Surface-mount 240-BFQFP package and RoHS compliance support standard production and assembly processes.
Why Choose AT6010H-2QC?
The AT6010H-2QC brings AT6000(LV) series architecture to applications that need reconfigurable, high-speed logic and significant I/O density in a compact surface-mount package. Its combination of 6,400 logic elements, extensive I/O, flexible clocking, and in-system reconfiguration supports adaptive hardware designs and compute offload use cases.
Designed with practical operating characteristics—5.0 V supply range (4.75 V–5.25 V), commercial temperature rating, and RoHS compliance—this device is suited for developers and procurement teams seeking a field-programmable solution that balances performance, integration and predictable power behavior.
Request a quote or submit a product inquiry to check pricing and availability for the AT6010H-2QC.

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