MT48LC4M32B2P-6A:L TR
| Part Description |
IC DRAM 128MBIT PAR 86TSOP II |
|---|---|
| Quantity | 752 Available (as of May 5, 2026) |
| Product Category | Memory |
|---|---|
| Manufacturer | Micron Technology Inc. |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 86-TSOP II | Memory Format | DRAM | Technology | SDRAM | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 128 Mbit | Access Time | 5.4 ns | Grade | Commercial | ||
| Clock Frequency | 167 MHz | Voltage | 3V ~ 3.6V | Memory Type | Volatile | ||
| Operating Temperature | 0°C ~ 70°C (TA) | Write Cycle Time Word Page | 12 ns | Packaging | 86-TFSOP (0.400", 10.16mm Width) | ||
| Mounting Method | Volatile | Memory Interface | Parallel | Memory Organization | 4M x 32 | ||
| Moisture Sensitivity Level | 3 (168 Hours) | RoHS Compliance | ROHS3 Compliant | REACH Compliance | REACH Unaffected | ||
| Qualification | N/A | ECCN | EAR99 | HTS Code | 8542.32.0002 |
Overview of MT48LC4M32B2P-6A:L TR – IC DRAM 128MBIT PAR 86TSOP II
The MT48LC4M32B2P-6A:L TR is a 128 Mbit volatile SDRAM organized as 4M × 32 with a parallel memory interface. It implements SDRAM architecture with a specified clock frequency of 167 MHz and an access time of 5.4 ns, delivering deterministic timing characteristics for systems that require defined parallel memory behavior.
This device is supplied in an 86-TSOP II (86-TFSOP, 0.400" / 10.16 mm width) package, operates from a 3.0 V to 3.6 V supply, and has an ambient operating temperature range of 0°C to 70°C. Write cycle time (word/page) is specified at 12 ns.
Key Features
- Memory Core
128 Mbit SDRAM organized as 4M × 32, providing a 32-bit data path in a single device. - Performance
Clock frequency of 167 MHz with an access time of 5.4 ns and a write cycle time (word/page) of 12 ns for predictable timing performance. - Interface
Parallel memory interface suited for designs requiring standard SDRAM parallel connectivity. - Power
Rated operating voltage from 3.0 V to 3.6 V to match common 3 V system rails. - Package
86-TSOP II (86-TFSOP, 0.400", 10.16 mm width) supplier device package for compact surface-mount deployment. - Environmental
Operating ambient temperature range specified from 0°C to 70°C (TA).
Unique Advantages
- 32‑bit memory organization: The 4M × 32 configuration provides a wide data path in a single device, simplifying parallel data bus design.
- Defined timing characteristics: 167 MHz clock and 5.4 ns access time support deterministic read/write timing for time-sensitive memory operations.
- Standard SDRAM interface: Parallel SDRAM connectivity enables integration with controllers designed for SDRAM signaling and timing.
- Compact TSOP II package: The 86-TSOP II package offers a space-efficient surface-mount form factor at a 10.16 mm width.
- 3.0–3.6 V supply compatibility: Matches common 3 V system rails for straightforward power-domain integration.
Why Choose IC DRAM 128MBIT PAR 86TSOP II?
The MT48LC4M32B2P-6A:L TR provides a straightforward SDRAM solution with explicit electrical and timing specifications, including a 167 MHz clock frequency, 5.4 ns access time, and a 12 ns write cycle time. Its 4M × 32 organization and parallel interface make it suitable for designs that require a single-device 32-bit memory data path and clearly defined SDRAM timing.
Packaged in an 86-TSOP II with a 3.0–3.6 V supply range and an operating ambient temperature of 0°C to 70°C, this device is intended for systems that require the listed capacity, form factor and operating conditions. It is a practical choice for engineers specifying SDRAM with these concrete electrical, timing and packaging parameters.
Request a quote or contact sales to obtain pricing, availability and lead-time information for MT48LC4M32B2P-6A:L TR.
