AT40K10-2AQC
| Part Description |
AT40K/KLV Field Programmable Gate Array (FPGA) IC 78 4608 576 100-TQFP |
|---|---|
| Quantity | 244 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 52 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 100-TQFP (14x14) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 100-TQFP | Number of I/O | 78 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 576 | Number of Logic Elements/Cells | 576 | ||
| Number of Gates | 20000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 4608 |
Overview of AT40K10-2AQC – Field Programmable Gate Array (FPGA), 78 I/O, 4,608‑bit RAM, 576 logic elements, 100‑TQFP
The AT40K10-2AQC is an SRAM-based FPGA from the AT40K family, offering a balance of on-chip logic, embedded memory and I/O density in a 100‑TQFP (14×14) surface-mount package. Designed for commercial applications, this device provides reprogrammable logic resources and on-chip RAM suitable for data-path acceleration, I/O interfacing and system glue logic.
As part of the AT40K series, the device leverages the family’s high-performance architecture—including global clocking and distributed 10 ns SRAM—to address applications such as DSP coprocessors, PCI-capable logic and adaptive designs where in-system reconfigurability and predictable timing are important.
Key Features
- Core performance – Family-level system speeds to 100 MHz and array multipliers >50 MHz, with internal tri-state capability in each cell for flexible logic implementation.
- Logic resources – 576 logic elements (cells) yielding approximately 20,000 usable gates for combinational and sequential logic functions.
- Embedded memory (FreeRAM) – 4,608 bits of distributed on-chip RAM in this device; the family supports flexible single/dual-port synchronous or asynchronous 10 ns SRAM configurations.
- I/O and package – 78 I/O pins in a 100‑TQFP (14×14) package; programmable output drive and pin-locking capabilities are supported at the family level.
- Supply and operating range – Nominal 5 V operation with supply range 4.75 V to 5.25 V; commercial operating temperature 0 °C to 70 °C.
- Clocking and control – Family-level support for 8 global clocks with programmable edge selection, distributed clock shutdown for power management, and global/asynchronous reset options.
- In-system reconfigurability – Cache Logic capability enables dynamic full or partial reconfiguration without data loss; unlimited re-programmability via serial or parallel modes is supported by the family.
- Standards and tool support – Family documentation cites PCI-compliant I/Os and integration with industry-standard design tools and IP cores for FIR filters, UARTs, PCI, FFT and other system functions.
- Compliance – RoHS compliant and supplied in a surface-mount 100‑TQFP package for standard SMT assembly.
Typical Applications
- DSP coprocessor implementations – Accelerate computation-intensive functions such as FIR filters, FFTs and transforms where on-chip multipliers and distributed RAM reduce external memory needs.
- Video and multimedia processing – Implement array multipliers, convolvers and coefficient storage for compression, decompression and signal-processing pipelines.
- PCI and high-speed I/O logic – Use programmable I/O and family-level PCI-compliant interfaces to implement bridge logic, protocol conversion and I/O expansion.
- Adaptive and reconfigurable systems – Benefit from in-system partial or full reconfiguration to update algorithms, coefficients or control logic without removing the device from the board.
Unique Advantages
- Balanced logic and memory – 576 logic elements plus 4,608 bits of distributed RAM provide a compact platform for mixed-control and data-path designs, reducing external component count.
- Deterministic performance – Family-level timing characteristics (system speeds to 100 MHz, 10 ns SRAM) enable predictable design closure for timing-sensitive subsystems.
- In-system flexibility – Cache Logic and serial/parallel reprogramming support allow design updates and adaptive behavior without hardware changes.
- Standard package and assembly – 100‑TQFP (14×14) surface-mount package simplifies integration into common PCB layouts and manufacturing flows.
- Commercial-grade, RoHS compliant – Suitable for commercial applications with RoHS compliance and a 0 °C to 70 °C operating range.
Why Choose AT40K10-2AQC?
The AT40K10-2AQC combines mid-range logic capacity with distributed on-chip RAM and a flexible clocking architecture, making it well-suited for commercial designs that require reprogrammable logic, embedded memory and reliable I/O in a space-efficient package. Its family-level features—PCI-capable I/Os, Cache Logic reconfigurability and industry toolchain support—help shorten development cycles for DSP, multimedia and I/O-intensive applications.
This device is a practical choice for engineers seeking a reprogrammable, commercially graded FPGA with clear electrical and thermal specifications (4.75–5.25 V supply, 0 °C to 70 °C) and a standard 100‑TQFP footprint for straightforward board integration and manufacturing.
If you would like pricing or availability, request a quote or submit an RFQ for the AT40K10-2AQC and our team will respond with current lead times and ordering information.

Date Founded: 1989
Headquarters: Chandler, Arizona, USA
Employees: 22,000+
Revenue: $8.349 Billion
Certifications and Memberships: ISO9001:2015, IATF16949:2016, AS 9100D