AT40K20-2CQC
| Part Description |
AT40K/KLV Field Programmable Gate Array (FPGA) IC 130 8192 1024 160-BQFP |
|---|---|
| Quantity | 532 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 160-PQFP (28x28) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 160-BQFP | Number of I/O | 130 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1024 | Number of Logic Elements/Cells | 1024 | ||
| Number of Gates | 30000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 8192 |
Overview of AT40K20-2CQC – AT40K/KLV Field Programmable Gate Array (FPGA) IC 130 I/O, 8,192-bit RAM, 1,024 Logic Elements, 160-BQFP
The AT40K20-2CQC is an SRAM-based FPGA from Microchip Technology’s AT40K/AT40KLV family, offering 1,024 logic elements and 8,192 bits of distributed on-chip RAM in a 160-BQFP surface-mount package. Designed for commercial-temperature applications, this device targets high-performance programmable logic tasks where on-chip memory, flexible I/O and reconfigurability are required.
Its architecture includes fast 10 ns distributed SRAM, support for multiple clock domains, and PCI-compliant I/O characteristics at 3V/5V signaling levels, making it suitable for compute- and I/O-intensive embedded designs and DSP-oriented coprocessor roles described in the family datasheet.
Key Features
- Core Logic — 1,024 logic elements (cells) delivering approximately 30,000 usable gates for implementing combinational and sequential logic.
- On-Chip Memory (FreeRAM) — 8,192 bits of distributed, 10 ns SRAM that can be configured as single-port or dual-port, synchronous or asynchronous memory for FIFOs, scratch pads and other buffering needs.
- Performance — Family-level performance indicators include system speeds to 100 MHz and array multipliers >50 MHz, with 10 ns flexible SRAM and internal tri-state capability in each cell.
- I/O — 130 I/O pins with 3V/5V capability and programmable output drive; I/O counts in the family support PCI-compliant implementations.
- Clocking — Up to eight global clocks with low-skew distribution, programmable edge transitions and distributed clock shutdown for power management (family feature).
- Package & Mounting — 160-BQFP surface-mount package (supplier device package: 160-PQFP 28×28) for high pin-count board designs.
- Power & Temperature — 5 V supply range (4.75 V to 5.25 V) and commercial operating temperature range of 0 °C to 70 °C.
- Standards & Tools — Family-level support for standard FPGA design flows and IP cores to accelerate implementation of DSP and system functions (as documented in the series datasheet).
- Compliance — RoHS-compliant device.
Typical Applications
- DSP Coprocessors — Implement FIR filters, FFTs, convolvers and other arithmetic functions using the device’s distributed RAM and array multiplier architecture for accelerated signal processing.
- Multimedia & Video Processing — Use on-chip memory and fast multiply structures to handle transformations and compression tasks in video and image pipelines.
- Embedded I/O Expansion — High I/O count and programmable output drive make the device suitable for bridging, protocol adaptation and custom peripheral interfaces in embedded systems.
- Adaptive & Reconfigurable Designs — Leverage the family’s Cache Logic dynamic partial/full reconfigurability and unlimited reprogramming modes to update algorithms or coefficients in-system.
Unique Advantages
- Flexible Embedded RAM: Distributed 10 ns FreeRAM can be instantiated as single- or dual-port memory without consuming separate logic macros, enabling efficient buffering and state storage.
- High I/O Density: 130 I/O pins with 3V/5V capability and programmable drive simplify interfacing to a wide range of legacy and modern peripherals.
- Reconfigurability: Series-level Cache Logic support for in-system partial or full reconfiguration enables adaptive designs and fast updates without losing retained data.
- Fast Arithmetic Support: Array multiplier architecture and high-speed internal routing support computationally intensive functions for DSP and multimedia workloads.
- Standard Package for Dense Designs: 160-BQFP (160-PQFP 28×28 footprint) balances pin count and board routing for compact, high-density implementations.
- Commercial-Grade Reliability: Specified for 0 °C to 70 °C operation with a defined 5 V supply range, suitable for mainstream embedded and commercial applications.
Why Choose AT40K20-2CQC?
The AT40K20-2CQC provides a balanced combination of on-chip memory, logic capacity and high I/O count in a 160-pin surface-mount package, making it well suited for designers needing programmable logic with fast embedded RAM and DSP-friendly resources. Its family-level features—such as 10 ns distributed SRAM, multi-clock support and dynamic reconfiguration—translate into practical advantages for adaptive, compute-heavy embedded systems.
This device is a fit for engineering teams developing commercial embedded applications, coprocessor acceleration modules and multimedia processing blocks that require a reprogrammable, SRAM-based FPGA with defined electrical and thermal limits and RoHS compliance.
Request a quote or submit an inquiry to get pricing and availability for the AT40K20-2CQC and discuss how it can fit into your next design cycle.

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