AX2000-CQ352M
| Part Description |
Axcelerator Field Programmable Gate Array (FPGA) IC 198 294912 352-BFCQFP with Tie Bar |
|---|---|
| Quantity | 369 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 44 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 352-CQFP (75x75) | Grade | Military | Operating Temperature | -55°C – 125°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 352-BFCQFP with Tie Bar | Number of I/O | 198 | Voltage | 1.425 V - 1.575 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 32256 | Number of Logic Elements/Cells | 32256 | ||
| Number of Gates | 2000000 | ECCN | 3A001A2C | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 294912 |
Overview of AX2000-CQ352M – Axcelerator Field Programmable Gate Array (FPGA) IC 198 294912 352-BFCQFP with Tie Bar
The AX2000-CQ352M is a military-grade Axcelerator FPGA from Microchip Technology based on the AX architecture and antifuse CMOS process. It delivers a nonvolatile, single-chip FPGA solution with architectural features intended for high-performance, secure embedded designs.
Built for applications that require deterministic timing, high-speed I/O and on-chip buffering, this device combines up to 2,000,000 equivalent system gates with embedded SRAM/FIFO, segmentable clocks and integrated PLLs to support demanding logic and interface requirements.
Key Features
- Core Performance 350+ MHz system performance and 500+ MHz internal performance are specified; integrated PLLs support a 14–200 MHz input range and frequency synthesis up to 1 GHz.
- Logic Capacity Approximately 2,000,000 equivalent system gates with 32,256 logic elements (cells), providing substantial capacity for complex logic integration.
- Embedded Memory & FIFOs Approximately 0.295 Mbits of embedded SRAM/FIFO (294,912 bits) with programmable FIFO control logic and variable-aspect 4,608-bit RAM blocks.
- I/O Flexibility 198 user I/Os with support for mixed-voltage operation (1.5V, 1.8V, 2.5V, 3.3V), bank-selectable I/Os, and multiple single-ended and differential standards including LVDS and LVPECL; LVDS-capable channels up to 700 Mb/s are supported.
- Security & Reliability Antifuse-based nonvolatile programming and FuseLock technology protect against reverse engineering and design theft; boundary-scan (JTAG) support enables standard test access.
- Package, Power & Thermal Surface-mount 352-BFCQFP package with tie bar (supplier package: 352-CQFP, 75×75). Core supply range is 1.425 V to 1.575 V. Rated operating temperature range is –55 °C to 125 °C. RoHS compliant.
- System Resources Segmentable clock resources and deterministic, user-controllable timing make the device suitable for designs that demand predictable timing behavior and in-system diagnostics via Microchip Silicon Explorer II.
Typical Applications
- Military & Defense Systems — Military-grade temperature range (–55 °C to 125 °C) and antifuse nonvolatile configuration make the device suitable for secure, rugged embedded electronics in defense applications.
- High-Speed Communications — LVDS-capable I/Os (up to 700 Mb/s) and high internal performance allow use in data transport, backplane interfacing and protocol bridging.
- Packet Buffering & Data Processing — Embedded SRAM/FIFO and programmable FIFO control logic support data buffering, packet handling and high-throughput streaming operations.
- Secure, Deterministic Control — Deterministic timing, segmentable clocks and on-chip PLLs suit real-time control systems that require predictable timing and secure, single-chip configuration.
Unique Advantages
- Single-chip, nonvolatile solution: Antifuse technology provides a one-time-programmable, nonvolatile configuration that avoids external configuration memory.
- High-performance timing and synthesis: Integrated PLLs, segmentable clocks and documented internal performance targets deliver precise timing control and frequency synthesis up to 1 GHz.
- Flexible multi-standard I/Os: Mixed-voltage, bank-selectable I/Os and support for both single-ended and differential standards simplify interfacing across a wide range of peripherals and signaling environments.
- Security features: FuseLock programming technology helps protect IP against reverse engineering and design theft.
- Robust packaging and thermal range: Surface-mount 352-BFCQFP packaging and a –55 °C to 125 °C operating range support deployment in temperature-challenging and mission-critical environments.
- Integrated memory and FIFO control: Nearly 295 kbits of embedded RAM with programmable FIFO logic reduces external memory requirements for many buffering and streaming applications.
Why Choose AX2000-CQ352M?
AX2000-CQ352M positions a high-capacity, high-performance Axcelerator FPGA into designs that require nonvolatile configuration, deterministic timing and robust I/O flexibility. Its combination of approximately 2,000,000 equivalent system gates, embedded SRAM/FIFO, integrated PLLs and security features makes it well suited for secure communications, data processing and military-grade embedded systems.
The device provides long-term design value through antifuse nonvolatile programming, comprehensive I/O options and support for in-system diagnostics, enabling designers to consolidate logic, reduce external components and maintain secure, predictable operation in demanding environments.
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