F59L1G81LB-25TG2M

1Gb NAND Flash
Part Description

SLC NAND Flash, 1Gbit, 3.3V, x8, 25ns, 48‑pin TSOPI

Quantity 1,744 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerESMT
Manufacturing StatusMP
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device PackageTSOPI-48Memory FormatFLASHTechnologyNAND Flash - SLC
Memory Size1 GbitAccess Time20 nsGradeCommercial
Clock FrequencyN/AVoltage2.7V ~ 3.6VMemory TypeNon-Volatile
Operating Temperature0°C – 70°CWrite Cycle Time Word Page350 µsPackaging48-TSOPI
Mounting MethodSurface MountMemory InterfaceParallelMemory Organization128M x 8
Moisture Sensitivity Level3RoHS ComplianceCompliantREACH ComplianceREACH Unknown
QualificationN/AECCNEAR99HTS Code8542.32.00.71

Overview of F59L1G81LB-25TG2M – SLC NAND Flash, 1Gbit, 3.3V, x8, 25ns, 48‑pin TSOPI

The F59L1G81LB-25TG2M is a 1.074 Gbit single-level cell (SLC) NAND flash device organized as 128M x 8 with spare area. It implements a parallel x8 NAND interface at a 3.3V supply range (2.7V–3.6V) and is offered in a 48‑pin TSOPI surface-mount package.

Designed for solid-state mass storage and embedded memory applications, the device combines page and block architecture, on-chip data registers and cache features, and hardware protection options to support boot and storage use cases where endurance, data retention and predictable electrical characteristics are required.

Key Features

  • Memory & Organization 1.074 Gbit capacity organized as 128M × 8 with an additional spare area (4M × 8). Page size is (2K + 64) bytes and block size is (128K + 4K) bytes.
  • Performance Access time specified at 20 ns; serial access 25 ns (datasheet). Page program and cache program operations are supported to improve program throughput.
  • Program / Erase Timing Write cycle time (word/page) listed as 350 µs; datasheet lists typical program and erase timing details for planning programming and maintenance operations.
  • Interface Parallel command/address/data multiplexed I/O port with x8 data bus for direct parallel connection in embedded designs.
  • Power Nominal 3.3V operation with an input range of 2.7V to 3.6V for flexible power-supply integration.
  • Reliability & Data Integrity SLC NAND cell design with endurance specified at 100K program/erase cycles and data retention of 10 years. ECC requirement indicated as 1 bit per 528 bytes.
  • System & Boot Support Features include automatic page 0 read at power-up and boot-from-NAND support to simplify system boot and firmware storage.
  • Package & Temperature Surface-mount TSOPI-48 package (12 mm × 20 mm, 0.5 mm pitch) and a commercial operating temperature range of 0 °C to 70 °C. RoHS compliant.

Typical Applications

  • Embedded Storage Use as local non-volatile storage for firmware, file systems and application data in embedded devices that require SLC durability and retention.
  • Boot Memory Supports boot-from-NAND and automatic page 0 read at power-up for systems that store boot code or initial firmware images in NAND flash.
  • Solid‑State Mass Storage Suited for compact solid-state storage implementations where block/ page management and reliable P/E endurance are needed.

Unique Advantages

  • SLC Endurance: Endurance rated at 100K program/erase cycles and 10 years data retention provide long-term reliability for storage and firmware applications.
  • Flexible Voltage Window: 2.7V–3.6V operating range enables straightforward integration with common 3.3V system rails.
  • Parallel x8 Interface: Multiplexed command/address/data I/O simplifies host interfacing in parallel NAND designs.
  • Boot and Power-Up Features: Automatic page 0 read at power-up and boot-from-NAND support reduce system initialization complexity.
  • Package Options: Available in a compact TSOPI-48 surface-mount package for space-constrained boards with standard pitch and board-mount processes.

Why Choose F59L1G81LB-25TG2M?

The F59L1G81LB-25TG2M positions itself as a reliable SLC NAND solution for embedded and solid-state storage designs requiring predictable endurance and long-term data retention. Its 128M × 8 organization with spare area, page and block architecture, and on-chip cache/program features support efficient data streaming, firmware updates and boot operations.

This device is suited to engineers and procurement teams building commercial-grade products that need SLC reliability, a parallel x8 interface, a commercial temperature rating, and a compact TSOPI-48 package. The documented program/erase and read behaviors enable deterministic integration into firmware and storage subsystems.

Request a quote or submit a product inquiry to receive pricing and lead‑time information for the F59L1G81LB-25TG2M.

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