A80960HA33SL2GY
| Part Description |
i960 Microprocessor IC i960 1 Core, 32-Bit 33MHz 168-PGA |
|---|---|
| Quantity | 1,620 Available (as of October 8, 2026) |
| Product Category | Microprocessors |
|---|---|
| Part Series | i960 Hx |
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Core Processor | i960 | Device Package | 168-PGA | ECCN | 3A991A2 | ||
|---|---|---|---|---|---|---|---|
| Grade | Commercial | Graphics Acceleration | No | HTS Code | 8542.31.0001 | ||
| Moisture Sensitivity Level | Not Applicable | Mounting Method | Through Hole | Mounting Type | Through Hole | ||
| Number of Cores/Bus Width | 1 Core, 32-Bit | Operating Temperature | 0°C ~ 85°C (TC) | Package / Case | 168-PGA | ||
| RAM Controllers | DRAM | REACH Compliance | REACH Unknown | RoHS Compliance | RoHS non-compliant | ||
| Speed | 33MHz | Supplier Device Package | 168-PGA | Voltage – I/O | 3.3V |
Overview of A80960HA33SL2GY – IC MPU I960 33MHz 168PGA
The A80960HA33SL2GY is a single-core 32‑bit microprocessor based on the Intel i960 architecture, offered in a 168‑pin PGA through‑hole package. It operates with a 33 MHz core clock and a 3.3 V I/O supply, and is supplied as a commercial‑grade device with an operating range of 0 °C to 85 °C.
Designed for embedded applications that require on‑chip floating point support and high internal bandwidth, this device combines an integrated FPU, on‑chip caches and RAM, and a flexible external bus architecture to support a range of system designs.
Key Features
- Core & Architecture Single i960 core, 32‑bit parallel load/store architecture with an on‑chip register cache and 16 global + 16 local registers for efficient context handling.
- Performance 33 MHz core clock (80960HA variant) with documented capability to issue up to 150 million instructions per second and high internal bandwidth (1.28 Gbyte at 80 MHz) for accelerated code and data throughput.
- On‑Chip Memory Integrated 16 KB four‑way set‑associative instruction cache, 8 KB four‑way set‑associative data cache, and 2 KB general‑purpose RAM to reduce external memory accesses.
- Floating Point & Memory Controller Integrated FPU and DRAM controller support to simplify system design and reduce external component count.
- Bus & External Bandwidth 32‑bit demultiplexed burst bus with per‑byte parity generation/checking, programmable wait states, and an external bandwidth specification of 160 Mbyte/s (40 MHz option).
- Interrupts & Timers High‑speed interrupt controller supporting up to 240 external interrupts with 31 programmable priorities and a separate non‑maskable interrupt pin; dual on‑chip 32‑bit timers with auto‑reload and one‑shot modes.
- System & Debug Guarded memory unit with user/supervisor read/write/execute protection and JTAG support (IEEE 1149.1) for boundary scan and on‑board debug.
- Power & I/O 3.3 V supply voltage with 5 V tolerant inputs and TTL‑compatible outputs for flexible interfacing with mixed‑voltage systems.
- Package & Mounting 168‑pin PGA package supplied for through‑hole mounting, suited to legacy or serviceable board designs.
- Commercial Grade & Compliance Commercial temperature grade (0 °C to 85 °C) and RoHS compliant.
Typical Applications
- Embedded systems 32‑bit processing with on‑chip FPU and caches for control, coordination, and compute tasks in embedded platforms.
- Legacy or serviceable board designs 168‑pin PGA through‑hole package enables repairability and compatibility with existing daughterboard or socketed implementations.
- Systems requiring deterministic timers and interrupts Dual 32‑bit timers and a high‑speed interrupt controller support real‑time event handling and priority management.
Unique Advantages
- Integrated floating point unit: Reduces need for an external FPU, lowering BOM and simplifying software support for floating‑point computation.
- On‑chip caches and RAM: 16 KB instruction cache, 8 KB data cache and 2 KB general RAM improve execution locality and reduce external memory bandwidth requirements.
- High internal and external bandwidth: 1.28 Gbyte internal bandwidth (80 MHz) and a 32‑bit demultiplexed burst bus with up to 160 Mbyte/s external bandwidth enable robust data movement for demanding embedded workloads.
- Flexible interrupt and timer resources: Support for up to 240 external interrupts and dual 32‑bit timers simplifies real‑time control and complex interrupt handling.
- 3.3 V operation with 5 V tolerant inputs: Facilitates integration into mixed‑voltage environments while maintaining low‑voltage power rails.
- JTAG and memory protection: IEEE 1149.1 JTAG support and a guarded memory unit provide improved debug access and memory protection features for system integrity.
Why Choose A80960HA33SL2GY?
The A80960HA33SL2GY pairs a proven i960 32‑bit core with on‑chip floating point, cache, and RAM resources to deliver a compact, highly integrated processor option for embedded designs that require deterministic control, efficient memory subsystem performance, and flexible I/O interfacing. Its 3.3 V operation, 5 V tolerant inputs, and through‑hole 168‑PGA package make it suitable for systems where serviceability and mixed‑voltage compatibility matter.
Offered as a commercial‑grade, RoHS‑compliant device with documented interrupt, timer, and bus features, this part is a practical choice for designers seeking a balanced combination of compute capability, system integration, and deployment readiness in embedded applications.
Request a quote or submit an inquiry to receive availability, lead‑time, and pricing information for A80960HA33SL2GY.

Date Founded: 1968
Headquarters: Santa Clara, California, USA
Employees: 130,000+
Revenue: $54.23 Billion
Certifications and Memberships: ISO9001:2015, ISO14001:2015, ISO17025:2017, ISO27001:2022, ISO45001:2018, ISO50001:2018