MC68EN302AG20BT
| Part Description |
M68000 Microprocessor IC M683xx 1 Core, 8/16-Bit 20MHz 144-LQFP (20x20) |
|---|---|
| Quantity | 1,292 Available (as of October 8, 2026) |
| Product Category | Microprocessors |
|---|---|
| Part Series | MC68 |
| Manufacturer | NXP USA Inc. |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Co-Processors/DSP | Communications; RISC CPM | Core Processor | M68000 | Device Package | 144-LQFP (20x20) | ||
|---|---|---|---|---|---|---|---|
| ECCN | EAR99 | Ethernet | 10Mbps (1) | Graphics Acceleration | No | ||
| HTS Code | 8542.31.0001 | Moisture Sensitivity Level | 3 (168 Hours) | Mounting Method | Surface Mount | ||
| Mounting Type | Surface Mount | Number of Cores/Bus Width | 1 Core, 8/16-Bit | Operating Temperature | 0°C ~ 70°C (TA) | ||
| Package / Case | 144-LQFP | RAM Controllers | DRAM | REACH Compliance | REACH Unaffected | ||
| RoHS Compliance | ROHS3 Compliant | Speed | 20MHz | Supplier Device Package | 144-LQFP (20×20) | ||
| Voltage – I/O | 5.0V |
Overview of MC68EN302AG20BT – IC MPU M683XX 20MHZ 144LQFP
The MC68EN302AG20BT from NXP Semiconductors is an integrated M68000-based multiprotocol microprocessor featuring a single 8/16-bit core running at 20 MHz. This device combines on-chip Ethernet and DRAM controller capabilities with serial communications and DMA resources, targeting embedded systems that require integrated communications and memory control.
Key platform attributes include 5 V I/O, a 144-LQFP (20 × 20 mm) package, RoHS compliance and an operating temperature range of 0 °C to 70 °C.
Key Features
- Core and Performance — M68000 microcoded core, single 8/16-bit processor core running at 20 MHz with 5 V I/O.
- Integrated Ethernet Controller — Ethernet MAC compatible with IEEE 802.3, 16-bit interface to the 68000 bus, supporting up to 10 Mb/s (20 Mb/s full-duplex) with on-chip transmit and receive FIFOs.
- On-Chip DMA and Buffer Management — Separate DMA channels for Ethernet transmit and receive, on-chip descriptors and dual-port RAM for buffer descriptors to reduce processor bus bandwidth requirements.
- Robust Ethernet Features — 128-byte transmit and receive FIFOs, automatic internal retransmission and automatic internal flushing of receive FIFO during collisions to minimize CPU and bus intervention.
- DRAM Controller — Integrated DRAM controller supporting parity and address multiplexing for external bus masters; glueless DRAM interfacing for simplified memory designs.
- Serial and Communications Peripherals — Includes multiple serial communication channels (three SCCs plus additional serial channels) and a RISC communications processor (CPM) for protocol handling and offload.
- Debug and Test — IEEE 1149.1 JTAG-compliant test support for board-level boundary scan and debug.
- Package and Environment — 144-LQFP surface-mount package (20 × 20 mm), RoHS compliant, operating temperature 0 °C to 70 °C.
Typical Applications
- Embedded Communications and Networking — On-chip Ethernet, DMA channels and buffer descriptors enable networked embedded controllers and protocol-handling devices.
- Communications Equipment — Multiple SCCs and a RISC CPM provide hardware support for protocol processing and serial communication offload.
- Memory-Intensive Embedded Systems — Integrated DRAM controller with parity support suits systems requiring on-board DRAM management and external bus master access.
- Industrial and Control Systems — 5 V I/O and comprehensive peripheral integration support legacy and new designs that combine control and communications functions.
Unique Advantages
- Highly Integrated Solution: Ethernet controller, DRAM controller, DMA channels, serial channels and CPU core are all on-chip, reducing BOM and board complexity.
- Ethernet Offload and Robustness: Dedicated Ethernet DMA channels, FIFOs and automatic retransmit/flush features reduce CPU and bus load during network activity.
- Efficient Buffer Management: On-chip descriptors and dual-port RAM for buffer descriptors lower processor bus bandwidth requirements and streamline data movement.
- Flexible Memory Support: DRAM controller with parity and external bus master addressing simplifies memory interfacing and supports reliability features.
- Production-Test Support: IEEE 1149.1 JTAG compliance facilitates boundary-scan testing and board-level debug.
- Standards-Based Ethernet: IEEE 802.3 compatibility and a 16-bit bus interface make integration with existing 68000-based system architectures straightforward.
Why Choose MC68EN302AG20BT?
The MC68EN302AG20BT positions itself as a compact, integrated multiprotocol processor ideal for embedded designs that need on-chip Ethernet and DRAM control alongside serial communications and DMA resources. Its integration reduces external component count and simplifies board design while the on-chip buffer management and DMA channels lower processor and bus loading during network transfers.
This device is suitable for engineers and procurement teams building networked embedded systems, communications equipment, and memory-driven controllers that require a combination of communications peripherals, DRAM support and production-test capability in a 144-LQFP, RoHS-compliant package.
Request a quote or submit an inquiry to obtain pricing and availability for the MC68EN302AG20BT and to discuss volume, lead times, and delivery options.

Date Founded: 2006
Headquarters: Eindhoven, North Brabant, Netherlands
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