MC68EN302AG25BT

IC MPU M683XX 25MHZ 144LQFP
Part Description

M68000 Microprocessor IC M683xx 1 Core, 8/16-Bit 25MHz 144-LQFP (20x20)

Quantity 977 Available (as of October 8, 2026)
Product CategoryMicroprocessors
Part SeriesMC68
ManufacturerNXP USA Inc.
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeContact Us
Datasheet

Specifications & Environmental

Co-Processors/DSPCommunications; RISC CPMCore ProcessorM68000Device Package144-LQFP (20x20)
ECCNEAR99Ethernet10Mbps (1)Graphics AccelerationNo
HTS Code8542.31.0001Moisture Sensitivity Level3 (168 Hours)Mounting MethodSurface Mount
Mounting TypeSurface MountNumber of Cores/Bus Width1 Core, 8/16-BitOperating Temperature0°C ~ 70°C (TA)
Package / Case144-LQFPRAM ControllersDRAMREACH ComplianceREACH Unaffected
RoHS ComplianceROHS3 CompliantSpeed25MHzSupplier Device Package144-LQFP (20×20)
Voltage – I/O5.0V

Overview of MC68EN302AG25BT – IC MPU M683XX 25MHz 144LQFP

The MC68EN302AG25BT is an NXP Semiconductors microprocessor based on the M68000 core, implemented as a single 8/16-bit core running at 25 MHz. It is an integrated multiprotocol processor variant that combines a M68000 core with on-chip communications peripherals including an Ethernet controller and a DRAM controller, aimed at embedded communications and control applications.

This device targets embedded systems that require integrated Ethernet, serial channels, DMA and on-chip memory support, providing a compact, surface-mount 144-LQFP (20×20) package and standard 5 V I/O operation within an ambient temperature range of 0 °C to 70 °C.

Key Features

  • Core M68000 microprocessor core; single 8/16-bit core operating at 25 MHz.
  • Power and I/O 5 V I/O voltage specification and surface-mount 144-LQFP (20×20) supplier device package.
  • Ethernet Controller On-chip Ethernet controller with a 16-bit interface, IEEE 802.3 programming model compatibility, support up to 10 Mb/s (20 Mb/s full-duplex), separate 128-byte transmit and receive FIFOs, and dedicated transmit and receive DMA channels.
  • Memory and DRAM Controller Integrated DRAM controller with support for parity and address muxing for external bus masters; on-chip dual-port RAM and on-chip buffer descriptors to reduce bus bandwidth requirements.
  • Peripherals and DMA Multiple DMA channels (including dedicated Ethernet DMA channels), serial communication channels (SCCs), general-purpose DMA, timers and a microcoded communications RISC/CPM coprocessor for communications handling.
  • System Integration On-chip buffer descriptor control, automatic retransmission and receive-FIFO flushing for Ethernet, dynamic bus sizing support and IEEE 1149.1 JTAG compliance for test/debug.
  • Environmental & Mechanical RoHS compliant; operating temperature range 0 °C to 70 °C; surface-mount 144-LQFP package suitable for compact embedded assemblies.
  • Additional Interfaces Includes GCI and other serial/peripheral interfaces as part of the integrated communications feature set.

Typical Applications

  • Embedded Communications Modules — Use the integrated M68000 core, communications RISC/CPM and multiple serial channels for protocol handling and serial link management.
  • Ethernet-Enabled Control Units — On-chip Ethernet MAC with dedicated DMA and FIFOs supports networked control and monitoring at 10 Mb/s (20 Mb/s full-duplex).
  • Memory-Backed Embedded Systems — Built-in DRAM controller with parity support and dual-port RAM simplifies designs that require local buffering and descriptor storage.
  • Multiprotocol Gateways — Combines serial controllers, DMA channels and Ethernet to implement compact protocol conversion and gateway functions in a single device.

Unique Advantages

  • Integrated Ethernet Subsystem — IEEE 802.3–compatible Ethernet controller with dedicated DMA and FIFOs offloads frame handling from the CPU, reducing bus overhead.
  • On-Chip DRAM Controller — Eliminates the need for an external DRAM controller, supports parity and external bus masters to simplify memory subsystem design.
  • Dedicated DMA and Descriptor Support — On-chip buffer descriptors and multiple DMA channels lower processor bus bandwidth requirements and improve data throughput for communications tasks.
  • Compact, Surface-Mount Package — 144-LQFP (20×20) package provides a small footprint for embedded board-level integration while supporting up to 25 MHz operation.
  • Built-In Test and Debug — IEEE 1149.1 JTAG compliance for boundary-scan and debug capability during development and production test.
  • Standards-Based Design — Ethernet and peripheral programming models follow established MC68302-style conventions to aid software integration.

Why Choose MC68EN302AG25BT?

The MC68EN302AG25BT brings together an M68000 core, integrated Ethernet and DRAM controllers, multiple DMA channels and serial communications features in a single 144-LQFP device. This level of integration reduces external component count and simplifies board design for embedded communications, networked control and multiprotocol gateway applications.

Designed for developers who need a compact, standards-based embedded processor with on-chip peripheral support, the device offers a mix of system functionality and testability (IEEE 1149.1) that supports robust designs and streamlined development cycles.

Request a quote or submit an RFQ to obtain pricing and lead-time information for the MC68EN302AG25BT for your next embedded communications design.

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