ORT8850H-1BMN680C

The ORT8850H-1BMN680C is a Field-Programmable System-on-a-Chip (FPSC) combining reconfigurable FPGA logic and integrated high-speed backplane transceivers. Built on Lattice's ORCA architecture, this device targets communications and system designs that require multi-channel serial links alongside substantial programmable logic.

Key capabilities include eight-channel SERDES backplane transceivers with built-in clock and data recovery, approximately 16,192 logic elements, and roughly 0.15 Mbits of embedded memory. The device is supplied in a 680-FPBGA (35×35) package and is RoHS compliant.

Key Features

• Integrated FPGA Logic  Approximately 16,192 logic elements and 2,024 PFUs (programmable function units) to implement custom logic, protocol handling, and application-specific functions.
• Embedded Memory  Approximately 0.15 Mbits of on-chip RAM (151,552 total RAM bits) for buffering, packet handling, and state storage.
• High-Speed Backplane Transceivers  Eight SERDES channels operating up to 850 Mbits/s per channel (aggregate up to 6.8 Gbits/s) with built-in Clock and Data Recovery (CDR) for clockless high-speed interfaces across a backplane or board-to-board links.
• Protocol and Framing Support  On-chip primitives and logic for SONET functionality including scrambling/descrambling, framing and transport overhead handling; protocol-independent framers and common networking framers are supported per device family documentation.
• System Resources and Gates  Device provides up to 899,000 system gates for implementing complex systems combining transceivers and programmable logic.
• I/O and Connectivity  297 user I/O pins to support broad peripheral and interface connectivity in system designs.
• Power and Package  Supports supply voltages from 1.425 V to 3.6 V; supplied in a 680-BBGA surface-mount package (680-FPBGA, 35×35 mm).
• Commercial Grade and Environmental  Commercial operating temperature range of 0 °C to 70 °C and RoHS compliant.

Typical Applications

• Backplane and Multiboard Communication: Implement high-density backplane links with clockless high-speed channels and on-chip CDR to simplify clock domain and board-to-board timing.
• Network Termination and Transport Interfaces: Use integrated SONET framing, scrambling/descrambling, and transport overhead handling to implement configurable network termination and protocol logic.
• High-Speed Protocol Bridging: Combine the FPGA fabric and SERDES to build configurable bridges such as PCI-to-PCI half-bridge implementations or other high-throughput bus link solutions.
• Custom Framing and Packet Processing: Leverage programmable logic and embedded RAM for protocol-independent framers, packet handling, and application-specific overhead processing.

Unique Advantages

• Integrated SERDES and FPGA Fabric: Combines eight high-speed transceiver channels with substantial programmable logic to reduce component count and simplify system architecture.
• High Logic Capacity: Approximately 16,192 logic elements and up to ~899K system gates enable complex protocol engines and custom logic alongside transceiver cores.
• Flexible I/O and Packaging: 297 user I/Os and a 680-FPBGA (35×35) package support dense system routing and a wide range of peripheral connections.
• Broad Voltage Range: Operates from 1.425 V to 3.6 V to accommodate varied system power domains and interfacing requirements.
• Designed for Communication Systems: Built-in SONET features, framers, and clock/data recovery are tailored to network and backplane applications that require integrated transport handling.
• Standards-Conscious Design Flow: Support for Lattice development tools and FPSC design kits is indicated in product documentation to help accelerate design and integration.

Why Choose ORT8850H-1BMN680C?

The ORT8850H-1BMN680C is positioned for engineers building communication-centric systems that need a combination of multi-channel serial transceivers and substantial programmable logic on a single device. Its integrated CDR-enabled backplane transceivers, large logic element count, significant I/O, and embedded memory make it well-suited for configurable network interfaces, backplane termination, and high-speed protocol bridging.

For design teams needing a compact, RoHS-compliant solution in a 680-FPBGA package, this device provides a balance of logic capacity, serial bandwidth, and interfacing flexibility while aligning with Lattice's documented FPSC design flow and development tool support.

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