ORT8850H-1BMN680I

The ORT8850H-1BMN680I is an ORCA® Field-Programmable System Chip (FPSC) from Lattice Semiconductor that combines FPGA logic with integrated high-speed backplane transceivers. It integrates a programmable FPGA fabric with eight serial transceiver channels and built-in clock and data recovery (CDR), enabling configurable high-speed interconnect and protocol handling for system-level designs.

Designed for industrial applications, the device targets backplane communications, protocol termination and custom transport logic where dense logic, substantial I/O and multi-gigabit aggregate throughput are required.

Key Features

• FPGA Logic Capacity — 16,192 logic elements providing programmable fabric for custom logic, protocol engines and system glue.
• Embedded Memory — Approximately 0.15 Mbits of on-chip RAM (151,552 total RAM bits) for buffering, framers and packet handling.
• High-Speed Transceivers — Eight backplane transceiver channels, each up to 850 Mbits/s (aggregate up to 6.8 Gbits/s) with built-in clock and data recovery in standard-cell logic.
• I/O Density — 297 user I/Os to support wide parallel interfaces, control planes and peripheral connectivity.
• System Gate Scale — Approximately 899,000 FPGA system gates for complex system-level implementations.
• Power and Voltage Flexibility — Supported supply range from 1.425 V to 3.6 V to accommodate a range of system power architectures.
• Package — 680-ball FPBGA package (35 × 35 mm) for high density surface-mount assembly.
• Industrial Temperature Range — Rated for operation from −40 °C to 85 °C for industrial-class deployments.
• Mounting — Surface-mount device suitable for standard PCB assembly processes.
• RoHS Compliant — Conforms to RoHS requirements.

Typical Applications

• Backplane Communication Systems — Built-in eight-channel transceivers and CDR make the device suitable for configurable backplane link terminations and high-speed board-to-board channels.
• Network Termination and Framing — Use the programmable fabric and embedded memory for SONET/SDH framing, pointer management and transport overhead handling.
• High-Speed Data Bridges — Implement PCI-to-PCI or other multi-gigabit interconnect bridges using the integrated transceivers and logic resources.
• Custom Protocol Engines — Develop protocol-independent framers, ATM/PoS processing or HDLC/IP interfacing using the FPGA fabric and available I/Os.

Unique Advantages

• Integrated Transceivers and Logic: Combines eight SERDES channels with programmable FPGA fabric to reduce external components and simplify high-speed interface design.
• Substantial Logic and Memory: 16,192 logic elements and roughly 0.15 Mbits of embedded memory enable complex protocol handling and buffering on-chip.
• High I/O Count: 297 user I/Os provide flexibility for wide bus interfaces, multi-lane connection topologies and control plane access.
• Industrial Reliability: Rated for −40 °C to 85 °C operation and supplied in a robust 680-FPBGA package suitable for industrial environments.
• Flexible Supply Range: Operates across a broad voltage range (1.425 V to 3.6 V) to fit varied system power designs.
• Proven Architecture: Architecture includes clock recovery and SONET-related functions exposed in standard-cell logic to simplify multi-board clocking and protocol implementations.

Why Choose ORT8850H-1BMN680I?

The ORT8850H-1BMN680I positions itself as a field-programmable system chip that brings together dense programmable logic, embedded memory and high-speed backplane transceivers in a single solution. Its combination of 16,192 logic elements, nearly 899,000 system gates and eight 850 Mbits/s transceiver channels provides the resources needed for complex protocol processing, high-bandwidth bridging and configurable network termination.

This device is well suited to engineering teams building industrial backplane systems, network interface modules or custom protocol engines who need on-chip transceivers, abundant I/O and industrial temperature support. The ORT8850H-1BMN680I supports scalable designs while reducing external component count and simplifying board-level interconnect.

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