MIMX9351AVTYMAB

The MIMX9351AVTYMAB is a microprocessor IC from the i.MX 9351 family featuring dual Arm® Cortex®-A55 application cores and a general-purpose Arm® Cortex®-M33 core. The device integrates a neural processing unit (NPU) for machine learning inference and a rich set of I/O and security features to support connected embedded designs.

Designed for edge compute and human‑machine interfaces, the MIMX9351AVTYMAB targets smart home, building control, contactless HMI, IoT edge and industrial applications where balanced application performance, real‑time processing, and integrated security are required.

Key Features

• Core and CPU architecture  Dual Arm® Cortex®-A55 application cores (64‑bit) plus a Cortex®-M33 real‑time/low‑power core. Cortex‑A55 cores operate up to 1.7 GHz and the Cortex‑M33 operates up to 250 MHz.
• Neural Processing Unit (NPU)  Integrated NPU with 256 MACs (operating up to 1.0 GHz) optimized for integer neural network workloads to accelerate on‑device inference.
• Memory and storage  External memory interface supports LPDDR4/LPDDR4X with inline ECC and up to 2 GByte addressable DDR memory space. Flexible flash and SD options include support for eMMC 5.1 (HS400 DDR), SDXC, and SDIO host controllers.
• Display and image interfaces  Display and camera support includes LCD, LVDS, MIPI‑DSI and MIPI‑CSI. The image sensor interface (ISI) supports runtimes up to 2K horizontal resolution and pixel rates up to 200 Mpixel/s with on‑chip image processing and scaling.
• Connectivity  Dual 1 Gbps Ethernet controllers (GBE), one controller supports Time Sensitive Networking (TSN) for low‑latency gateway and control applications.
• USB and peripheral I/O  Two USB 2.0 ports plus multiple high‑speed and legacy peripheral controllers for flexible system integration.
• Security and system protection  Hardware features include boot security, cryptography primitives, eFuse, a true random number generator (RNG), secure RTC and tamper detection options to support secure boot and runtime protection.
• On‑chip memory and boot ROM  Dedicated boot ROM and on‑chip RAM resources for secure and reliable booting of both Cortex‑A55 and Cortex‑M33 subsystems.
• Mounting and compliance  Surface mount device and RoHS compliant.
• Graphics acceleration  No dedicated graphics acceleration is included.

Typical Applications

• Smart Home and Building Control  Edge compute and connectivity for automated environmental control, sensor aggregation, and local decision making.
• Contactless HMI  Drive camera-based interfaces and touchless interaction with on‑device image processing and ML inference via the integrated NPU.
• IoT Edge Devices  Local analytics and gateway functions leveraging dual Gigabit Ethernet and secure boot capabilities to process data at the edge.
• Industrial Control  Real‑time monitoring and control tasks using the Cortex‑M33 for deterministic processing alongside Cortex‑A55 application cores.

Unique Advantages

• Heterogeneous compute  Combines high‑performance Cortex‑A55 cores, a real‑time Cortex‑M33 core, and an integrated NPU to split application, control and ML workloads efficiently.
• Integrated ML acceleration  On‑chip NPU with 256 MACs accelerates integer neural network inference to reduce system latency and offload the application cores.
• Robust connectivity  Dual 1 Gbps Ethernet controllers (one with TSN) plus USB and multiple SD/eMMC options simplify networked and gateway designs.
• Secure by design  Comprehensive hardware security features including boot security, cryptography, eFuse and RNG support secure boot and trusted operations.
• Image and display support  MIPI CSI/DSI, LCD and LVDS interfaces with a capable ISI that handles up to 2K resolution and high pixel rates for camera and display applications.
• Memory reliability  LPDDR4/LPDDR4X support with inline ECC and flexible flash interfaces provide data integrity and scalable storage performance.

Why Choose MIMX9351AVTYMAB?

The MIMX9351AVTYMAB positions itself as a balanced, integrated processor for embedded systems requiring application‑level performance, deterministic control, and on‑device ML acceleration. Its combination of dual Cortex‑A55 cores, a Cortex‑M33 real‑time core, and an NPU enables designs that separate user‑facing workloads, control loops, and inference tasks efficiently within a single device.

This part is suited to engineers building smart home, building automation, contactless HMI, IoT edge and industrial systems who need secure boot, robust connectivity, and image sensor support while minimizing external components and system complexity.

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