MIMX9352AVTYMAB
| Part Description |
Microprocessor IC |
|---|---|
| Quantity | 745 Available (as of October 8, 2026) |
| Product Category | Microprocessors |
|---|---|
| Part Series | i.MX 9352 |
| Manufacturer | NXP USA Inc. |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 2 Weeks |
| Datasheet |
Specifications & Environmental
| Co-Processors/DSP | Multimedia; NEON™ MPE | Core Processor | ARM® Cortex®-A55, ARM® Cortex®-M33 | Display & Interface Controllers | LCD, LVDS, MIPI-CSI, MIPI-DSI | ||
|---|---|---|---|---|---|---|---|
| ECCN | N/A | Ethernet | GBE (2) | Graphics Acceleration | No | ||
| HTS Code | N/A | Moisture Sensitivity Level | N/A | Mounting Method | Surface Mount | ||
| Number of Cores/Bus Width | 2, 1 Core, 64-Bit | Qualification | Automotive | RAM Controllers | LPDDR4 | ||
| REACH Compliance | REACH Unknown | RoHS Compliance | Unknown | USB | USB 2.0 (2) |
Overview of MIMX9352AVTYMAB – Microprocessor IC
The MIMX9352AVTYMAB is a high-integration microprocessor from NXP’s i.MX 9352 family that combines application-class CPUs, a real-time core, and dedicated neural acceleration for edge compute tasks. It features dual Arm® Cortex®-A55 application cores alongside an Arm® Cortex®-M33 real-time core and an on-chip NPU to address mixed workloads in connected devices.
Targeted for smart home, building control, contactless HMI, IoT edge and industrial applications, the device delivers a balance of compute performance, low-power real-time control, secure boot and robust connectivity to simplify system design and accelerate time to market.
Key Features
- Core processing — Dual Arm® Cortex®-A55 processors (up to 1.7 GHz) with 32 KB L1 I-cache, 32 KB L1 D-cache, 64 KB per-core L2 cache and a 256 KB cluster L3 cache; supports Arm® v8.2-A 64-bit architecture, NEON™ MPE and VFPv4-D16 floating point.
- Real-time subsystem — Arm® Cortex®-M33 running up to 250 MHz with FPU, MPU, NVIC and 256 KB tightly coupled memory (TCM); two-way set-associative 16 KB system and 16 KB code caches for deterministic control tasks.
- Neural Processing Unit (NPU) — 256 MACs operating up to 1.0 GHz (2 OPS/MAC); targets 8-bit and 16-bit integer RNN workloads and supports 8-bit weights for on-device ML inference.
- Memory subsystem — 16-bit DRAM interface supporting LPDDR4X/LPDDR4 with inline ECC and up to 2 GByte DDR memory space; on-chip RAM 640 KB and dual 256 KB boot ROMs for Cortex-A55 and Cortex-M33; FlexSPI flash with XIP support.
- Imaging and display — Image Sensor Interface (ISI) supporting standard pixel formats up to 2K horizontal resolution and pixel rates up to 200 Mpixel/s with image processing (downscaling, color space conversion, interlaced→progressive); display controllers for LCD, LVDS, MIPI-CSI and MIPI-DSI.
- Connectivity — Dual 1 Gbps Ethernet controllers (one with Time Sensitive Networking support), two USB 2.0 ports, three uSDHC interfaces (including eMMC 5.1, SDXC and SDIO) and CAN‑FD for robust control networks.
- Security and system reliability — Boot security, cryptography, eFuse, hardware random number generator, secure RTC and tamper detection; parity/ECC protection on L1/L2 caches and TLB RAMs.
- Mounting and compliance — Surface mount device and RoHS compliant.
Typical Applications
- Smart Home and Building Control — Central compute for building automation, sensor consolidation and local decision-making leveraging dual A55 cores and deterministic M33 control.
- Contactless HMI — Responsive user interfaces with camera input and image processing handled by the ISI and application cores.
- IoT Edge Compute — On-device ML inference using the NPU for low-latency analytics and reduced cloud dependency.
- Industrial Gateway and Networking — Dual 1 Gbps Ethernet (with TSN support) and CAN‑FD enable low-latency, resilient gateway designs and protocol bridging.
- General-purpose Compute — Paired high-performance A55 cores and real-time M33 provide a versatile platform for mixed workloads and edge services.
Unique Advantages
- Highly integrated compute — Dual Cortex‑A55 application cores plus Cortex‑M33 real-time core consolidate application and control domains on a single device, reducing BOM and board complexity.
- Edge ML acceleration — Dedicated 256‑MAC NPU accelerates integer neural network inference for local analytics and responsiveness.
- Comprehensive imaging pipeline — ISI supporting up to 2K resolution and up to 200 Mpixel/s with on-chip processing simplifies camera integration for HMI and vision tasks.
- Deterministic networking — Dual 1 Gbps Ethernet controllers with TSN support and CAN‑FD provide options for low-latency, time-aware and robust networked systems.
- Memory integrity and secure boot — Inline ECC for LPDDR4, cache parity/ECC and dedicated boot ROMs support system reliability and secure start-up.
- Flexible storage and I/O — Multiple uSDHC ports (eMMC 5.1, SDXC, SDIO), FlexSPI XIP and dual USB 2.0 ports enable diverse storage and peripheral choices.
Why Choose MIMX9352AVTYMAB?
The MIMX9352AVTYMAB combines application-class performance, real-time control and on-chip neural acceleration in a single, power-optimized package. Its balance of dual Cortex‑A55 cores, Cortex‑M33 real-time processing and an NPU makes it suited for designs that require mixed criticality workloads, on-device ML, and extensive sensor or camera support.
This device fits designers targeting smart home, building control, contactless HMI, IoT edge and industrial gateway applications who need a compact, feature-rich platform with secure boot, robust connectivity and a comprehensive memory and imaging subsystem.
Request a quote or contact sales to discuss availability, lead times and integration support for the MIMX9352AVTYMAB.

Date Founded: 2006
Headquarters: Eindhoven, North Brabant, Netherlands
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