EP20K100BC356-3
| Part Description |
APEX-20K® Field Programmable Gate Array (FPGA) IC 252 53248 4160 356-LBGA |
|---|---|
| Quantity | 480 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 356-BGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 356-LBGA | Number of I/O | 252 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 416 | Number of Logic Elements/Cells | 4160 | ||
| Number of Gates | 263000 | ECCN | 3A001A2A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 53248 |
Overview of EP20K100BC356-3 – APEX-20K Field Programmable Gate Array (FPGA), 356-LBGA
The EP20K100BC356-3 is an Intel APEX-20K series FPGA delivering mid-range programmable logic, embedded memory and flexible I/O in a compact 356-LBGA package. It implements the APEX 20K family MultiCore architecture, which integrates look-up table (LUT) logic, product-term logic and embedded system blocks for memory and combinatorial functions.
Designed for commercial embedded applications, this device targets designs that require a balance of logic capacity, on-chip RAM and extensive I/O in a surface-mount BGA package. Its combination of logic elements, RAM and clock management features supports a wide range of control, interface and data-buffering tasks.
Key Features
- Device family & architecture – APEX 20K MultiCore architecture integrating LUT logic, product-term logic and embedded system blocks (ESBs) for memory and combinatorial functions.
- Logic capacity – 4,160 logic elements and approximately 263,000 system gates to implement mid-density programmable logic designs.
- Embedded memory – Approximately 0.053 Mbits (53,248 bits) of on-chip RAM, with ESB structures usable for FIFOs, dual-port RAM and CAM-like functions.
- I/O resources – 252 user I/O pins supporting flexible interfacing; family-level MultiVolt I/O support enables connection to a range of external voltage domains.
- Clock management – Family features include multiple PLLs and up to eight global clocks, with programmable clock phase/delay and clock multiplication/division capabilities.
- Package & mounting – 356-LBGA (35 × 35 mm) surface-mount package for compact board-level integration.
- Power and supply – Device supply range 2.375 V to 2.625 V and family-level low-power design options, including ESB power-saving modes.
- Operating range & compliance – Commercial grade operation from 0 °C to 85 °C; RoHS-compliant.
Typical Applications
- Embedded control systems – Use the EP20K100BC356-3 to implement custom control logic, state machines and processing pipelines where integrated logic and on-chip RAM reduce external component count.
- Interface bridging and protocol conversion – 252 I/Os and MultiVolt support allow flexible interfacing between different voltage domains and peripheral standards in commercial equipment.
- Memory buffering and FIFO functions – ESB-based embedded memory is suitable for FIFOs, dual-port RAM and buffering between asynchronous domains.
- Prototyping and development – Mid-range logic density and a compact BGA package make the device appropriate for proof-of-concept designs and evaluation in commercial product development.
Unique Advantages
- Highly integrated solution: Combines 4,160 logic elements with on-chip memory to lower BOM and simplify board design compared with discrete logic plus external RAM.
- Flexible I/O connectivity: 252 user I/Os and family-level MultiVolt I/O support enable direct interfacing to multiple voltage domains and a variety of peripheral standards.
- On-chip memory versatility: ESB structures support FIFO, dual-port RAM and CAM-style uses, helping to implement buffering and table-based functions with minimal external parts.
- Robust clocking features: Multiple PLLs and programmable clock management support complex timing and multi-clock designs without extensive external timing circuitry.
- Compact, assembly-friendly package: 356-LBGA (35×35) surface-mount package provides a dense footprint for space-constrained commercial products.
- Commercial-grade reliability and compliance: Rated for 0 °C to 85 °C operation and RoHS-compliant for commercial product builds.
Why Choose EP20K100BC356-3?
The EP20K100BC356-3 positions itself as a mid-density FPGA option within the APEX-20K family, offering a balanced mix of logic elements, embedded memory and extensive I/O in a compact 356-LBGA package. Its MultiCore architecture and ESB-based memory enable designers to consolidate logic and buffering functions on chip, reducing system complexity and component count.
This device is well suited to commercial embedded designs that require programmable logic, flexible interfacing and reliable operation across standard commercial temperature ranges. The combination of integrated memory, clock management features and a high I/O count delivers a practical platform for prototyping and production use where scalability and vendor-backed ecosystem support are important.
Request a quote or submit an inquiry to get pricing and availability for the EP20K100BC356-3 and support for your next design project.

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