EP20K100EBC356-3
| Part Description |
APEX-20KE® Field Programmable Gate Array (FPGA) IC 246 53248 4160 356-LBGA |
|---|---|
| Quantity | 1,400 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 356-BGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 356-LBGA | Number of I/O | 246 | Voltage | 1.71 V - 1.89 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 416 | Number of Logic Elements/Cells | 4160 | ||
| Number of Gates | 263000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 53248 |
Overview of EP20K100EBC356-3 – APEX-20KE® Field Programmable Gate Array (FPGA) IC 246 53248 4160 356-LBGA
The EP20K100EBC356-3 is an APEX-20KE family field programmable gate array (FPGA) in a 356-ball LBGA package designed for commercial applications. It integrates a MultiCore architecture combining look-up table (LUT) logic and embedded system blocks (ESBs) to implement logic and on-chip memory functions.
This device targets designs that need a mid-range FPGA resource set—including 4,160 logic elements, 246 user I/Os, and 53,248 bits of on-chip RAM—while providing flexible I/O options and clock management for system-level integration and mixed-voltage interfacing.
Key Features
- Core Architecture MultiCore architecture with LUT logic and embedded system blocks (ESBs) for register‑intensive and memory-related functions.
- Logic Resources 4,160 logic elements and a maximum gate count listed as 263,000, providing capacity for mid-range programmable logic implementations.
- Embedded Memory 53,248 total RAM bits on-chip for FIFOs, dual-port RAM and content-addressable memory (CAM) implementations.
- I/O and Standards Support 246 user I/O pins with MultiVolt I/O interface support; programmable clamps and slew-rate control plus individual tri-state enable for flexible signal interfacing.
- Clock Management Flexible clock resources including up to four phase-locked loops (PLLs), built-in low-skew clock tree, up to eight global clocks, and programmable clock phase/delay features.
- High-Speed Interfaces Architectural support for high-speed external memories such as DDR SDRAM and ZBT SRAM, PCI-compliant 3.3‑V operation, and differential signaling like LVDS.
- Power and Supply Internal voltage supply range of 1.71 V to 1.89 V and MultiVolt I/O levels to interface with a range of external devices.
- Package & Thermal 356-LBGA (35 × 35 mm BGA) surface-mount package rated for commercial operation from 0 °C to 85 °C.
- Compliance RoHS compliant.
Typical Applications
- Communications & Networking Implement protocol bridging, packet processing, or memory interface logic using the device’s flexible I/O and embedded RAM capabilities.
- Memory Controllers & Interfaces Use the on-chip RAM and high-speed interface support for DDR SDRAM or ZBT SRAM control and buffering.
- Embedded System Integration Leverage ESBs for FIFOs, dual-port RAM and CAM to build compact system-on-programmable-chip (SOPC) designs.
- High-Speed I/O Designs Deploy LVDS and high-frequency bidirectional I/O paths for data acquisition, SERDES front-ends, or high-throughput signaling.
Unique Advantages
- MultiCore Integration: Combines LUT-based logic and embedded system blocks to implement both register-intensive and memory-intensive functions within a single device.
- Balanced Resource Set: 4,160 logic elements with 53,248 bits of embedded RAM and 246 I/Os provide a practical mid-range resource mix for many system designs.
- Flexible Clocking: Multiple PLLs, global clock signals and programmable phase/delay features enable precise clock domain management for complex designs.
- Mixed-Voltage Interfacing: MultiVolt I/O support and programmable I/O features allow direct interfacing to a variety of external voltage domains.
- Compact, Surface-Mount Package: 356-LBGA (35 × 35 mm) package supports high-density PCB layouts while maintaining a commercial temperature range for general-purpose applications.
Why Choose EP20K100EBC356-3?
The EP20K100EBC356-3 offers a practical combination of logic, embedded memory, and I/O flexibility within the APEX-20K family architecture. Its MultiCore design and ESB support make it suitable for designs that require integrated memory functions alongside LUT-based logic.
This device is well suited to engineers and teams building mid-range programmable solutions that need mixed-voltage I/O capability, configurable clock management, and on-chip RAM for buffering and control logic. As a member of the APEX 20K family, it provides a clear path for scaling within related device options.
Request a quote or submit your requirements to receive pricing and availability for the EP20K100EBC356-3. Our team can provide a tailored quote to support your project timeline and volume needs.

Date Founded: 1968
Headquarters: Santa Clara, California, USA
Employees: 130,000+
Revenue: $54.23 Billion
Certifications and Memberships: ISO9001:2015, ISO14001:2015, ISO17025:2017, ISO27001:2022, ISO45001:2018, ISO50001:2018