EP20K160ETC144-2X
| Part Description |
APEX-20KE® Field Programmable Gate Array (FPGA) IC 88 81920 6400 144-LQFP |
|---|---|
| Quantity | 471 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 144-TQFP (20x20) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 144-LQFP | Number of I/O | 88 | Voltage | 1.71 V - 1.89 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 640 | Number of Logic Elements/Cells | 6400 | ||
| Number of Gates | 404000 | ECCN | 3A001A2A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 81920 |
Overview of EP20K160ETC144-2X – APEX-20KE® Field Programmable Gate Array (FPGA), 6,400 logic elements, ~0.082 Mbits RAM, 88 I/O, 144-LQFP
The EP20K160ETC144-2X is an APEX-20KE® family FPGA in a 144-LQFP package designed for commercial embedded logic applications. It integrates 6,400 logic elements, approximately 81,920 bits of embedded RAM, and 88 user I/O pins to enable compact system integration for communication, control, and data-path functions. With surface-mount packaging, RoHS compliance, and a commercial temperature range, this device is suited for a wide range of board-level digital designs.
Key Features
- Core Logic — 6,400 logic elements (LEs) and approximately 404,000 gates deliver flexible programmable logic density for mid-range designs.
- Embedded Memory — Approximately 81,920 bits (≈0.082 Mbits) of on-chip RAM for FIFOs, dual-port RAM, and other storage functions.
- I/O Count & Flexibility — 88 user I/O pins with MultiVolt I/O interface support (series-level support for 1.8 V, 2.5 V, 3.3 V, and 5.0 V) to interface with a variety of external components and voltage domains.
- Clocking and Timing — Series architecture provides flexible clock management including multiple PLLs, a low-skew clock tree, and features for clock phase/delay control to support synchronous system designs.
- High-speed Interfaces — Series-level support for high-speed memory interfaces (including DDR SDRAM and ZBT SRAM), LVDS signaling, and PCI-compatible operation for 3.3 V systems.
- Power and Supply — Core supply specified at 1.71 V to 1.89 V and designed for low-power operation consistent with the APEX-20K family.
- Package & Mounting — 144-LQFP (supplier package 144-TQFP, 20 × 20 mm) surface-mount package suitable for standard PCB assembly.
- Environmental & Grade — Commercial grade device with operating temperature range 0 °C to 85 °C and RoHS compliance.
Typical Applications
- Communication Interfaces — Implement protocol bridging, parallel-to-serial conversion, and LVDS-enabled links leveraging the device’s I/O flexibility and embedded memory.
- Embedded Control — Use for real-time control logic, glue logic, and peripheral aggregation where mid-range logic density and multiple I/O voltages are required.
- Memory Interface Glue — Serve as an interface controller for DDR SDRAM or ZBT SRAM-based subsystems, using the device’s series-level support for high-speed memory connections.
- Prototyping & System Integration — Rapid implementation of custom IP, FIFOs, and combinatorial/regenerative logic using the family’s LUT and embedded system block capabilities.
Unique Advantages
- Balanced Logic Density: 6,400 logic elements and ~404,000 gates provide a mid-range resource set ideal for embedded and communication designs without excess overhead.
- On-Chip Memory for Data Path Efficiency: Approximately 81,920 bits of embedded RAM enable compact FIFO and buffer implementations that reduce external memory dependency.
- Multi-Voltage I/O Flexibility: Series-level MultiVolt I/O support simplifies integration with diverse peripherals and legacy interfaces across multiple voltage domains.
- Versatile Clock Management: Built-in PLLs and a low-skew clock tree support complex synchronous designs and help manage clock distribution and phase adjustment on-chip.
- Surface-Mount, RoHS-Compliant Package: 144-LQFP surface-mount package aligns with standard PCB manufacturing processes and RoHS requirements for lead-free assembly.
Why Choose EP20K160ETC144-2X?
The EP20K160ETC144-2X positions itself as a practical, mid-density FPGA choice for designers needing a combination of logic elements, embedded RAM, and flexible I/O in a compact 144-LQFP package. Its defined core supply range (1.71–1.89 V), commercial temperature rating, and RoHS compliance make it suitable for mainstream embedded, communication, and interface applications where modular system integration and on-chip memory are required.
Engineers building prototypes, board-level controllers, and interface bridges will find the device’s blend of programmable logic, on-chip RAM, and clock/I/O capabilities a fit for projects that require reliable logic resources and straightforward board-level implementation.
Request a quote or submit an inquiry to obtain pricing, lead time, and availability for the EP20K160ETC144-2X APEX-20KE® FPGA for your next design.

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