LAV-AT-G70-2LFG676I

LATTICE AVANT MID-RANGE GENERAL
Part Description

Avant™-G Field Programmable Gate Array (FPGA) IC 298 4239360 637000 676-BBGA, FCBGA

Quantity 94 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time8 Weeks
Datasheet

Specifications & Environmental

Device Package676-FCBGA (27x27)GradeIndustrialOperating Temperature-40°C – 100°C
Package / Case676-BBGA, FCBGANumber of I/O298Voltage820 mV
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity LevelN/ANumber of LABs/CLBsN/ANumber of Logic Elements/Cells637000
Number of GatesN/AECCNN/AHTS CodeN/A
QualificationN/ATotal RAM Bits4239360

Overview of LAV-AT-G70-2LFG676I – Avant™-G Field Programmable Gate Array (FPGA) IC

The LAV-AT-G70-2LFG676I is an Avant™-G FPGA IC from Lattice Semiconductor Corporation built on the Lattice Avant platform architecture. The device integrates programmable functional units, on-chip memory, clocking resources, and high-density I/O in a 676-FCBGA package for surface-mount assembly.

With 637,000 logic element cells, approximately 4.24 Mbits of embedded memory, and 298 I/O, this industrial-grade FPGA targets demanding embedded and system designs that require large programmable logic capacity, flexible memory modes, and extensive I/O and interface capabilities while operating across an industrial temperature range.

Key Features

  • Logic Capacity — 637,000 logic element cells provide extensive programmable logic resources for complex digital implementations.
  • Embedded Memory — Total on-chip RAM of 4,239,360 bits (approximately 4.24 Mbits) with sysMEM features including single, dual and pseudo-dual port modes, FIFO modes, memory cascading and RAM initialization/ROM operation.
  • I/O Density — 298 programmable I/O pins with a sysI/O banking scheme and programmable I/O cell (PIC) blocks that include input, output and tri-state register functionality.
  • Clocking and Timing — Comprehensive clocking structure that includes on‑chip oscillator, PLL, global (GCLK), regional (RCLK), edge (ECLK) clocks, PHYCLK, clock synchronizers/dividers, dynamic clock select/control and DLL delay features.
  • High-Speed Interfaces — Integrated SERDES and PCS blocks with SERDES/PMA, Multi‑Protocol PCS (MPPCS) and Multi‑Protocol PHY (MPPHY) integration; DDR memory support with DDRPHY and DQS grouping.
  • Programmable Functional Units — Architecture details such as Programmable Functional Unit (PFU) blocks and slices enable flexible logic mapping and modes of operation.
  • sysDSP and Accelerators — Dedicated sysDSP resources are included for signal processing and arithmetic functions described in the platform overview.
  • Device Configuration & Reliability — Enhanced configuration options, JTAG support, and Single Event Upset (SEU) handling mechanisms are documented in the platform overview.
  • Package & Mounting — 676‑FCBGA (27×27) package case; surface mount mounting type suitable for standard PCB assembly processes.
  • Industrial Operating Range — Rated for operation from -40 °C to 100 °C; RoHS compliant.
  • Supply Voltage — Device supply specified at 820 mV.

Unique Advantages

  • Substantial Logic and Memory Integration: 637,000 logic element cells combined with ~4.24 Mbits of on-chip RAM reduce external component needs for many designs.
  • Versatile I/O and Interface Support: 298 I/O with programmable I/O cells and integrated SERDES/PCS blocks enable a wide range of interface topologies without adding discrete PHYs.
  • Flexible Clocking and Timing: Multiple on-chip clock resources (PLL, GCLK, RCLK, ECLK, PHYCLK) and dynamic clock controls simplify complex timing and multi‑clock-domain designs.
  • DDR Memory and PHY Support: DDRPHY and DQS grouping documented in the platform overview facilitate memory interface implementations using on‑chip PHY resources.
  • Industrial Temperature Capability: Rated from -40 °C to 100 °C for deployment in industrial environments where extended temperature operation is required.
  • Platform-Level Architecture: The Avant platform includes PFU blocks, sysDSP, and sysMEM capabilities described in the datasheet, providing a clear architectural foundation for system designers.

Why Choose LAV-AT-G70-2LFG676I?

The LAV-AT-G70-2LFG676I positions itself as a high-capacity FPGA option within the Lattice Avant platform, combining a large number of logic elements, sizeable on‑chip memory, extensive I/O and integrated high‑speed interface blocks in a single 676‑FCBGA package. Its documented clocking structure, memory modes, DDRPHY support, and configuration features give engineers a cohesive set of on‑chip resources to implement complex, multi‑domain digital systems.

This device is suitable for designs that require high programmable logic density, flexible embedded memory configurations, and a broad set of I/O and interface options, with RoHS compliance and an industrial operating temperature range supporting deployment in industrial applications.

Request a quote or submit a purchase inquiry to evaluate LAV-AT-G70-2LFG676I for your next design.

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