LCMXO1200C-3MN132C

The LCMXO1200C-3MN132C is a MachXO family non-volatile FPGA from Lattice Semiconductor, combining instant-on single-chip configuration with flexible FPGA-style logic. It provides 1200 logic elements and approximately 9.4 Kbits of on-chip RAM, making it suitable for glue logic, bus bridging/interfacing, power-up control and general control logic in commercial applications.

Designed for compact, low-power system designs, the device offers reconfigurable SRAM logic, background programming and system-level features such as JTAG boundary scan and an onboard oscillator to simplify integration and in-field updates.

Key Features

• Core Logic — 1200 logic elements to implement combinational and sequential logic for glue logic and control functions.
• On-chip Memory — Total on-chip RAM of 9,421 bits (approximately 9.4 Kbits) for embedded and distributed storage.
• I/O — 101 I/O pins available in a 132-ball CSPBGA (8×8 mm) package to support multiple external interfaces and dense board layouts.
• Non-volatile, Instant-on — Single-chip configuration with no external configuration memory required; instant-on operation and secure bitstream behavior.
• Reconfiguration & Programming — In-field reconfiguration capabilities, background programming of non-volatile memory, and JTAG programmability (IEEE 1149.1).
• Low-power Modes — Sleep mode support enabling up to 100× static current reduction for power-sensitive applications.
• Clocking — Includes up to one sysCLOCK PLL for clock multiply, divide and phase shifting.
• Power — Wide supply support with operating voltage range from 1.71 V to 3.465 V.
• Package & Temperature — 132-LFBGA (132-CSPBGA, 8×8) surface-mount package; commercial-grade operation from 0 °C to 85 °C.
• Standards & System Support — IEEE 1149.1 boundary scan and IEEE 1532 in-system programming support; onboard oscillator included.
• Compliance — RoHS compliant packaging.

Typical Applications

• Glue Logic — Implement combinational glue logic between processors, memories and peripherals with compact on-chip resources.
• Bus Bridging and Interfacing — Bridge and adapt between system buses and I/O standards using available I/O and programmable logic.
• Power-Up and Reset Control — Manage power sequencing, reset distribution and supervisory control leveraging instant-on behavior.
• Embedded Control and State Machines — Implement control logic, finite state machines and peripheral interfaces within a single non-volatile device.

Unique Advantages

• Single-chip non-volatile configuration: Eliminates the need for external configuration memory and enables immediate operation after power-up.
• Fast, field reconfiguration: Support for reconfigurable SRAM and background programming reduces downtime for in-field updates.
• Low-power operation: Sleep mode with significant static current reduction helps extend battery life or reduce system power draw.
• Compact package with ample I/O: 132-ball CSPBGA (8×8) offers 101 I/Os in a small footprint for dense board designs.
• System-level programmability: JTAG, IEEE 1532 in-system programming and an onboard oscillator simplify manufacturing and debug flows.

Why Choose LCMXO1200C-3MN132C?

The LCMXO1200C-3MN132C combines MachXO family non-volatile instant-on behavior with FPGA-style logic flexibility, making it a practical choice for commercial designs that require reliable glue logic, bus interfacing and in-field update capability. Its balanced mix of logic density, on-chip RAM and 101 I/Os in a compact 132-ball CSPBGA package supports space-constrained applications without sacrificing system-level features.

Engineers and buyers seeking a compact, reconfigurable, and RoHS-compliant solution for control and interface tasks will find the LCMXO1200C-3MN132C suited to projects that prioritize rapid startup, secure single-chip configuration and straightforward in-system programming.

Request a quote or submit a quote for the LCMXO1200C-3MN132C to begin procurement or for volume pricing information.