LCMXO3L-1300E-5UWG36CTR1K
| Part Description |
MachXO3 Field Programmable Gate Array (FPGA) IC 28 65536 1280 36-UFBGA, WLCSP |
|---|---|
| Quantity | 36 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 20 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 36-WLCSP (2.54x2.59) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 36-UFBGA, WLCSP | Number of I/O | 28 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | ROHS3 Compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 1 (Unlimited) | Number of LABs/CLBs | 160 | Number of Logic Elements/Cells | 1280 | ||
| Number of Gates | N/A | ECCN | EAR99 | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 65536 |
Overview of LCMXO3L-1300E-5UWG36CTR1K – MachXO3 Field Programmable Gate Array (FPGA) IC, 28 I/Os, 65,536-bit RAM, 1,280 Logic Elements, 36-WLCSP
The LCMXO3L-1300E-5UWG36CTR1K is a member of the MachXO3 family of non-volatile FPGAs. It provides a compact, surface-mount programmable logic solution with 1,280 logic elements and 65,536 bits of embedded RAM for implementing custom logic, glue functions, and low- to mid-density control and interface tasks.
Designed for compact system integration, this device offers a 36-WLCSP package, 28 I/O pins, and support for multi-time programmable configuration and on-chip system features described in the MachXO3 family datasheet.
Key Features
- Core Logic 1,280 logic elements (logic cells) for implementing combinational and sequential logic and small-scale state machines.
- Embedded Memory 65,536 bits of on-chip RAM suitable for small FIFOs, register files, and buffering.
- I/O and Interfaces 28 general-purpose I/O pins and programmable I/O cell architecture as detailed in the MachXO3 family documentation for flexible signal interfacing.
- On-Chip IP and Peripherals Family-level features include embedded hardened IP such as I²C and SPI cores, timers/counters, an on-chip oscillator, and user flash memory (UFM) as described in the datasheet.
- Configuration and Reconfiguration Non-volatile, multi-time programmable device configuration with TransFR reconfiguration and support for device configuration and boundary-scan testability outlined in the MachXO3 datasheet.
- Clocking Flexible on-chip clocking including PLL support (sysCLOCK PLLs) as provided in the family architecture for common clocking and timing needs.
- Package & Mounting 36-WLCSP (2.54 × 2.59 mm) surface-mount package for compact board designs and space-constrained applications.
- Power & Temperature Recommended supply range from 1.14 V to 1.26 V and an operating temperature range of 0 °C to 85 °C (commercial grade).
- Compliance RoHS-compliant.
Typical Applications
- Peripheral and Sensor Interfaces Use the device’s programmable I/O and embedded I²C/SPI IP cores to implement sensor hubs, bridge interfaces, and peripheral management logic.
- Control and Glue Logic Implement board-level control, protocol translation, and glue logic leveraging 1,280 logic elements and on-chip RAM for buffering and state management.
- Configuration and System Management Use non-volatile, multi-time programmable configuration and user flash memory for on-board configuration, system ID (TraceID), and small configuration stores.
Unique Advantages
- Compact, low-profile package: The 36-WLCSP footprint (2.54 × 2.59 mm) enables dense board layouts and small form-factor designs.
- Non-volatile, reprogrammable configuration: Multi-time programmable configuration removes the need for external volatile configuration memory in many use cases.
- Integrated peripheral IP: Hardened I²C and SPI cores plus timer/counter functions reduce firmware overhead and simplify interface implementations.
- Flexible clocking and timing: On-chip oscillator and sysCLOCK PLLs support common clocking schemes without adding external clock management components.
- Design-friendly memory and logic balance: 65,536 bits of RAM paired with 1,280 logic elements suits small FIFOs, buffering and control logic without excessive external RAM.
- Commercial-grade operating range: Specified for 0 °C to 85 °C operation and RoHS compliance for standard commercial product deployment.
Why Choose LCMXO3L-1300E-5UWG36CTR1K?
This MachXO3 family device delivers a balanced combination of compact packaging, non-volatile configuration, and embedded peripherals suitable for space-constrained electronic designs that require interface logic, board-level control, or system management functionality. The combination of 1,280 logic elements, 65,536 bits of RAM, and hardened IP blocks enables designers to consolidate components and simplify BOMs.
Choose this part for commercial designs where compact footprint, flexible I/O, on-chip configuration, and integrated peripheral support provide a practical path to reduce external components and accelerate system integration. The device is supported by the MachXO3 family architecture and documentation for predictable integration into embedded systems.
If you would like pricing, availability, or a formal quote for the LCMXO3L-1300E-5UWG36CTR1K, submit a quote request or request a product quote to receive current lead-time and ordering information.