LCMXO3L-1300E-6MG256C

IC FPGA 206 I/O 256CSFBGA
Part Description

MachXO3 Field Programmable Gate Array (FPGA) IC 206 65536 1280 256-VFBGA, CSPBGA

Quantity 1,440 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time20 Weeks
Datasheet

Specifications & Environmental

Device Package256-CSFBGA (9x9)GradeCommercialOperating Temperature0°C – 85°C
Package / Case256-VFBGA, CSPBGANumber of I/O206Voltage1.14 V - 1.26 V
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs160Number of Logic Elements/Cells1280
Number of GatesN/AECCN3A991DHTS Code8542.39.0001
QualificationN/ATotal RAM Bits65536

Overview of LCMXO3L-1300E-6MG256C – MachXO3 Field Programmable Gate Array, 1280 logic elements, 206 I/Os

The LCMXO3L-1300E-6MG256C is a MachXO3 family FPGA offered by Lattice Semiconductor. It implements a compact, non-volatile FPGA architecture with 1,280 logic elements and approximately 65,536 bits of embedded memory in a low-profile 256-VFBGA (256-CSFBGA, 9×9) package.

Designed for commercial-grade systems, this device delivers flexible on-chip clocking, programmable I/O, embedded hardened IP (including I²C and SPI cores), and multi-time programmable non-volatile configuration — making it suitable for control, interface, and integration tasks where a small-footprint FPGA is required.

Key Features

  • Core Logic — 1,280 logic elements to implement glue logic, control state machines, and small datapath functions.
  • Embedded Memory — Approximately 65,536 bits of on-chip RAM (sysMEM embedded block RAM) supporting single/dual/pseudo-dual port and FIFO modes as described in the MachXO3 family data sheet.
  • I/O Capacity & Flexibility — 206 user I/Os with high-performance, flexible I/O buffer architecture and pre-engineered source-synchronous I/O options.
  • Clocking and Timing — Flexible on-chip clocking and sysCLOCK phase-locked loops (PLLs) for system clock generation and domain management.
  • Embedded Hardened IP — Integrated hardened IP including I²C and SPI cores, and timer/counter functionality for common peripheral control tasks.
  • Non-volatile, Multi-time Programmable Configuration — On-chip non-volatile configuration memory and TransFR reconfiguration capability as part of the MachXO3 feature set.
  • Power and Package — Low-voltage core supply range of 1.14 V to 1.26 V; supplied in a surface-mount 256-VFBGA (256-CSFBGA, 9×9) package.
  • Commercial Grade and Environmental — Commercial operating temperature range of 0 °C to 85 °C and RoHS compliant.
  • System Support & Testability — Includes configuration and testing features referenced in the MachXO3 family documentation (boundary-scan testability and device configuration options).

Typical Applications

  • Interface Bridging & Glue Logic — Implement protocol translation, timing adaptation, and peripheral aggregation using the device’s I/O count and embedded logic resources.
  • Control and State Machines — Replace discrete logic or microcontroller offloads for system sequencing, configuration control, and simple real-time control tasks with the on-chip logic and timers.
  • Peripheral Integration — Use hardened I²C and SPI cores to integrate sensors and external devices while handling custom I/O and timing requirements.
  • Prototyping and Small FPGA Functions — Rapidly iterate small FPGA-based functions that require non-volatile configuration and compact packaging.

Unique Advantages

  • Non-volatile Configuration: Multi-time programmable on-chip non-volatile memory removes the need for external configuration flash for many applications.
  • Embedded Hardened IP: Built-in I²C, SPI and timer/counter IP reduce design time and BOM compared to building these functions from soft logic.
  • Compact, Low-Profile Package: 256-VFBGA (256-CSFBGA, 9×9) surface-mount package provides a small board footprint for space-constrained designs.
  • Flexible I/O and Clocking: High-performance I/O buffers, source-synchronous I/O support, and on-chip PLLs simplify timing and interface implementation.
  • Commercial Temperature and RoHS Compliance: Commercial operating range (0 °C to 85 °C) and RoHS compliance align with standard commercial product requirements.

Why Choose LCMXO3L-1300E-6MG256C?

This MachXO3 device combines a compact package, non-volatile configuration, and a balanced set of logic, memory, and I/O to address low- to mid-density FPGA needs in commercial applications. Its embedded hardened IP and flexible clocking reduce development effort for common interface and control tasks, while the surface-mount 256-VFBGA package supports compact board designs.

Choose this part when your design requires a small, commercially graded FPGA with built-in peripheral IP, moderate on-chip RAM, and a substantial I/O count — providing a scalable, supported option within the MachXO3 family architecture.

Request a quote or submit a purchase inquiry to get pricing and availability for the LCMXO3L-1300E-6MG256C. We can help provide volume pricing, lead-time information, and support for integration into your design.

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