LFE3-95EA-8FN672C

IC FPGA 380 I/O 672FPBGA
Part Description

ECP3 Field Programmable Gate Array (FPGA) IC 380 4526080 92000 672-BBGA

Quantity 134 Available (as of October 8, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time20 Weeks
Datasheet

Specifications & Environmental

Device Package672-FPBGA (27x27)GradeCommercialOperating Temperature0°C – 85°C
Package / Case672-BBGANumber of I/O380Voltage1.14 V - 1.26 V
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs11500Number of Logic Elements/Cells92000
Number of GatesN/AECCN3A991DHTS Code8542.39.0001
QualificationN/ATotal RAM Bits4526080

Overview of LFE3-95EA-8FN672C – ECP3 Field Programmable Gate Array (FPGA) IC 380 4526080 92000 672-BBGA

The LFE3-95EA-8FN672C is a commercial-grade FPGA from the Lattice ECP3 family, delivering a balanced combination of logic capacity, embedded memory, and I/O density in a 672-ball fpBGA package. Built on the ECP3 architecture, it targets high-volume, high-speed, cost-sensitive designs that require on-chip DSP resources, flexible I/O standards and multi-gigabit serial interfaces.

Key values include integrated SERDES and sysDSP capabilities, substantial on-chip RAM, and a compact 27×27 mm 672-FPBGA footprint — all supported by a 1.14 V to 1.26 V core supply and commercial temperature range for mainstream embedded applications.

Key Features

  • Logic Capacity — Provides 92,000 logic elements suitable for medium-to-high complexity designs that require significant programmable fabric.
  • Embedded Memory — Total on-chip RAM of 4,526,080 bits (approximately 4.53 Mbits) for buffering, packet handling and state storage.
  • I/O Density — 380 user I/Os enable wide parallel interfaces and flexible board-level connectivity.
  • Embedded SERDES — ECP3-series SERDES support data rates documented in the family datasheet from 150 Mbps to 3.2 Gbps for generic 8b10b, 10-bit and 8-bit SERDES modes, enabling multi-gigabit serial links.
  • sysDSP and DSP Slices — Family-level sysDSP architecture provides cascaded multiply-accumulate resources and wide ALU operations for signal processing tasks (refer to family datasheet for slice options and configurations).
  • Flexible sysI/O — Programmable I/O buffer support across a broad set of standards and on-chip termination options as described in the ECP3 family documentation.
  • Configuration and System Support — Supports SPI boot flash interface, dual-boot images, soft error detect macros and on-chip oscillator for initialization (family-level features).
  • Package and Mounting — 672-FPBGA (27×27 mm) surface-mount package (672-BBGA designation), suitable for compact board layouts.
  • Power and Temperature — Core voltage range 1.14 V to 1.26 V; commercial operating temperature range 0 °C to 85 °C.
  • Compliance — RoHS compliant.

Typical Applications

  • High-speed communications — Multi-gigabit SERDES and abundant I/O make the device suitable for protocol bridging, PHY interfacing, and serial link aggregation.
  • Video and broadcast systems — On-chip DSP resources and embedded memory support processing and buffering tasks required in video transport and formatting applications.
  • Networking and packet processing — Logic density and embedded RAM enable packet buffering, traffic management and custom packet processing engines.
  • Memory interface and bridging — Programmable sysI/O and dedicated DDR features support source-synchronous memory interfaces and buffering logic.

Unique Advantages

  • Balanced integration: 92,000 logic elements combined with approximately 4.53 Mbits of embedded memory reduces external component needs and simplifies PCB routing.
  • High I/O count: 380 user I/Os provide flexibility to implement wide parallel buses, multiple peripheral interfaces or high-pin-count system functions.
  • Multi-gigabit serial capability: Family-level SERDES support up to 3.2 Gbps enables high-bandwidth links without discrete transceivers.
  • DSP-oriented fabric: sysDSP architecture and multiply-accumulate resources accelerate signal processing tasks directly in the FPGA fabric.
  • Compact package: 672-FPBGA (27×27 mm) offers a compact form factor for space-constrained designs while preserving ample routing and I/O.
  • Commercial-grade reliability: Specified for 0 °C to 85 °C operation with RoHS compliance for mainstream embedded and networking applications.

Why Choose LFE3-95EA-8FN672C?

The LFE3-95EA-8FN672C positions itself as a versatile mid-to-high capacity FPGA option within the Lattice ECP3 family, combining 92,000 logic elements, significant on-chip RAM and 380 I/Os in a 672-ball fpBGA package. Its family-provided features — including embedded SERDES, sysDSP slices and flexible sysI/O — make it well suited for high-volume, high-speed, cost-sensitive designs that require integrated DSP and serial-link capabilities.

Design teams targeting networking, video, communications and memory-interface applications will find the device’s mix of programmable logic, embedded memory and multi-standard I/O useful for reducing BOM complexity and enabling compact board layouts while operating within commercial temperature and voltage ranges.

Request a quote or submit a procurement inquiry to start a design evaluation or to obtain pricing and availability information for the LFE3-95EA-8FN672C.

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