LFECP20E-3FN672C
| Part Description |
ECP Field Programmable Gate Array (FPGA) IC 400 434176 19700 672-BBGA |
|---|---|
| Quantity | 942 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FPBGA (27x27) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 400 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 2464 | Number of Logic Elements/Cells | 19700 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 434176 |
Overview of LFECP20E-3FN672C – ECP Field Programmable Gate Array (FPGA) IC 400 434176 19700 672-BBGA
The LFECP20E-3FN672C is a Lattice Semiconductor ECP-series field programmable gate array (FPGA) in a 672-ball BBGA (27 × 27 mm) package. It integrates 19,700 logic elements, approximately 434,176 bits of on-chip RAM, and 400 user I/Os to address mainstream and cost-sensitive FPGA designs.
Designed for applications that require a balance of logic density, on-chip memory and flexible I/O, the device operates from a 1.14 V to 1.26 V supply and is specified for commercial temperature operation (0 °C to 85 °C). It is RoHS compliant.
Key Features
- Logic Fabric Approximately 19,700 logic elements suitable for mid-range FPGA implementations and logic-intensive designs.
- Embedded Memory Approximately 434,176 bits of on-chip RAM (about 424 Kbits of EBR), providing block and distributed memory capacity for buffering, FIFOs and local storage.
- I/O Density 400 user I/Os in the 672-BBGA package to support complex board-level connectivity and multiple external interfaces.
- Package & Mounting 672-ball FPBGA (27 × 27 mm) package, surface-mount mounting for compact board integration.
- Power Low-voltage core operation with a supply range of 1.14 V to 1.26 V to match system power budgets requiring 1.2 V-class cores.
- Temperature & Grade Commercial grade operation, specified from 0 °C to 85 °C.
- Family-Level DSP Capability As a member of the LatticeECP family, the platform provides sysDSP blocks (family-level support of 4–8 blocks depending on device) for high-performance multiply–accumulate operations.
- Memory Interface Support Family-level dedicated DDR memory interface support implementing up to DDR400 (200 MHz) for external memory subsystems.
- Clocking & System Support Family-level support for up to four analog PLLs per device and system-level features including IEEE 1149.1 boundary scan and SPI boot flash interface.
- Standards-Compatible I/O The LatticeECP family supports a wide range of I/O standards (LVCMOS, LVTTL, SSTL, HSTL, PCI, LVDS, LVPECL, RSDS and others), enabling flexible interface choices for mixed-signal systems.
- Regulatory RoHS compliant.
Typical Applications
- Mainstream FPGA Systems Mid-range logic and control implementations where a balance of logic elements and on-chip memory is required.
- Cost-Sensitive Embedded Designs Systems that require optimized FPGA features and a compact BGA package to reduce BOM and board area.
- DSP Acceleration Signal-processing functions leveraging the family’s sysDSP blocks for multiply–accumulate workloads.
- Memory Interface Controllers Applications requiring dedicated DDR memory support up to DDR400 for external memory subsystems.
Unique Advantages
- Balanced Logic and Memory: About 19,700 logic elements combined with roughly 434,176 bits of embedded RAM provide a substantial on-chip resource mix for medium-complexity designs.
- High I/O Count in Compact Package: 400 user I/Os in a 27 × 27 mm 672-BBGA package enable dense connectivity without a large package footprint.
- Low-Voltage Core: 1.14 V–1.26 V supply aligns with 1.2 V-class power domains commonly used in modern systems.
- DDR Memory Support: Family-level dedicated DDR interface to support external memory at DDR400 rates, simplifying system memory integration.
- System Integration Features: Multiple PLLs, boundary-scan and SPI boot support facilitate system-level design, debug and board bring-up.
- RoHS Compliance: Meets environmental regulations for lead-free assembly and compliant product stacks.
Why Choose LFECP20E-3FN672C?
The LFECP20E-3FN672C places mid-range FPGA resources—nearly 20k logic elements, substantial on-chip RAM and 400 I/Os—into a compact 672-ball BGA package optimized for mainstream and cost-sensitive applications. Its 1.2 V-class core supply, commercial temperature grade and RoHS compliance make it suitable for a wide range of embedded system designs.
This device is appropriate for engineers seeking a balanced, scalable FPGA platform with family-level DSP and DDR interface capabilities, plus system-level features such as multiple PLLs and boundary-scan support to streamline development and integration.
Request a quote or submit a procurement inquiry to evaluate LFECP20E-3FN672C for your next design.