LIF-MD6000-6UWG36ITR1K

IC FPGA 17 I/O 36WLCSP
Part Description

CrossLink™ Field Programmable Gate Array (FPGA) IC 17 184320 5936 36-UFBGA, WLCSP

Quantity 1,432 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time20 Weeks
Datasheet

Specifications & Environmental

Device Package36-WLCSP (2.54x2.59)GradeIndustrialOperating Temperature-40°C – 100°C
Package / Case36-UFBGA, WLCSPNumber of I/O17Voltage1.14 V - 1.26 V
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level1 (Unlimited)Number of LABs/CLBs1484Number of Logic Elements/Cells5936
Number of GatesN/AECCNEAR99HTS Code8542.39.0001
QualificationN/ATotal RAM Bits184320

Overview of LIF-MD6000-6UWG36ITR1K – CrossLink™ FPGA, 36‑UFBGA WLCSP (Industrial)

The LIF-MD6000-6UWG36ITR1K is a CrossLink™ Field Programmable Gate Array (FPGA) IC from Lattice Semiconductor Corporation in a 36‑UFBGA WLCSP package. It implements a programmable fabric and system I/O features from the CrossLink family, delivering a compact, industrial‑grade FPGA for designs that require small form factor, low‑voltage operation and on‑chip programmable I/O.

Targeted at embedded and industrial applications, this device combines roughly 5,936 logic elements, embedded RAM, and dedicated CrossLink family blocks such as MIPI D‑PHY, programmable I/O banks, and on‑chip clocking and power management resources described in the CrossLink family datasheet.

Key Features

  • Logic Capacity — 5,936 logic elements for implementing custom logic, glue‑logic and peripheral interfaces.
  • Embedded Memory — Approximately 0.18 Mbits of on‑chip RAM (184,320 total RAM bits) to support FIFOs, buffers and small data structures.
  • Programmable I/O — 17 user I/O pins and programmable I/O banks as described in the CrossLink family documentation for flexible interface implementations.
  • Hardened Interface Blocks (CrossLink family) — Includes CrossLink architecture features such as MIPI D‑PHY blocks and programmable sysI/O buffers referenced in the family datasheet for camera and serial interfaces.
  • Power and Clocking Resources — On‑chip power management unit and sysCLK PLLs are part of the CrossLink family architecture for integrated power and clock control.
  • Operating Range — Industrial operating temperature from −40 °C to 100 °C and supply voltage range of 1.14 V to 1.26 V.
  • Package and Mounting — 36‑UFBGA WLCSP, supplier device package 36‑WLCSP (2.54 × 2.59 mm); surface mountable for compact board designs.
  • Regulatory — RoHS compliant.

Typical Applications

  • Camera and Vision Interfaces — Use the CrossLink family’s MIPI D‑PHY and programmable I/O to implement camera bridges, sensor interfaces and basic image preprocessing pipelines.
  • Embedded Video and Image Processing — Small FPGA fabric and on‑chip RAM support tight, low‑latency logic required for elementary video path processing and protocol translation.
  • Industrial Control and I/O Expansion — Industrial temperature grade and surface‑mount WLCSP package make this device suitable for compact control nodes, sensor aggregation and protocol conversion in industrial systems.

Unique Advantages

  • Compact WLCSP Footprint — 36‑UFBGA WLCSP (2.54 × 2.59 mm) minimizes PCB area, enabling dense system integration and space‑constrained designs.
  • Low‑Voltage Operation — 1.14 V to 1.26 V supply range supports low‑power system architectures and voltage‑constrained power domains.
  • Industrial Temperature Rating — Rated for −40 °C to 100 °C operation for deployment in industrial environments.
  • Integrated CrossLink Family Blocks — On‑chip MIPI D‑PHY, programmable I/O, PLL and power management resources reduce external component count by leveraging family features.
  • Right‑sized Logic and Memory — 5,936 logic elements and approximately 0.18 Mbits of embedded RAM provide a balanced resource set for glue logic, interface bridging and small processing tasks.
  • RoHS Compliant — Meets RoHS requirements for environmental compliance.

Why Choose LIF-MD6000-6UWG36ITR1K?

The LIF-MD6000-6UWG36ITR1K positions the CrossLink family in a compact, industrial‑grade FPGA offering a mix of programmable logic, embedded RAM and dedicated interface blocks. It is suited to designers needing a small‑footprint, low‑voltage FPGA with CrossLink family I/O and clocking features for camera interfaces, protocol bridging and embedded control tasks.

With RoHS compliance, a WLCSP package optimized for space‑sensitive boards, and documented CrossLink family resources (MIPI D‑PHY, programmable sysI/O, PLLs and PMU), this device provides a practical option for engineers seeking integrated interface capabilities and predictable operating ranges for industrial applications.

Request a quote or submit an inquiry to receive pricing and availability for the LIF-MD6000-6UWG36ITR1K. Our team can assist with part ordering and provide the CrossLink family datasheet and technical documentation upon request.

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