ORSO82G5-1FN680C
| Part Description |
ORCA® 4 Field Programmable Gate Array (FPGA) IC 372 113664 10368 680-BBGA |
|---|---|
| Quantity | 1,088 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 680-FPBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 680-BBGA | Number of I/O | 372 | Voltage | 1.425 V - 3.6 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1296 | Number of Logic Elements/Cells | 10368 | ||
| Number of Gates | 643000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 113664 |
Overview of ORSO82G5-1FN680C – ORCA® 4 Field Programmable Gate Array (FPGA) IC 372 113664 10368 680-BBGA
The ORSO82G5-1FN680C is an ORCA® Series 4 reconfigurable embedded System-on-a-Chip (SoC) FPGA optimized for high-speed backplane and board-to-board interfaces. Built with integrated high-speed SERDES channels and a substantial FPGA fabric, it targets applications requiring multi-gigabit serial links and flexible programmable logic for SONET and other backplane protocols.
This device combines eight integrated SERDES channels (0.6–2.7 Gbps) with clock-and-data-recovery (CDR) circuitry and a sizable programmable fabric, enabling configurable high-throughput interconnects, protocol handling, and custom packet or cell processing on a single surface-mount 680-BBGA package.
Key Features
- Series 4 FPGA architecture — Reconfigurable embedded SoC architecture with 10,368 logic elements for implementing protocol logic, custom datapaths, and control functions.
- High-speed SERDES — Eight integrated serial channels operating from 0.6 to 2.7 Gbps with built-in Clock and Data Recovery (CDR) to support high-speed backplane links and reduced clock routing complexity.
- Aggregate bandwidth — Designed to deliver aggregate serial bandwidth consistent with high-throughput backplane applications (ORSO82G5 family supports aggregate bandwidths referenced in the product family documentation).
- Embedded memory — Total on-chip RAM of 113,664 bits (approximately 0.114 Mbits), with the datasheet noting two 4K × 36 RAM blocks in the embedded core that are accessible by FPGA logic.
- I/O and package — 372 user I/O pins in a 680-ball FBGA package (680-FPBGA, 35 × 35 mm) for high pin-count system interconnects; surface-mount mounting type.
- Logic and gate capacity — Approximately 643,000 system gates (per family gate-count range) enabling substantial on-chip integration of protocol and application logic.
- Power and thermal — Supports a wide supply range from 1.425 V to 3.6 V and is rated for commercial operating temperatures from 0 °C to 70 °C.
- Standards and compliance — RoHS-compliant manufacturing for environmental regulatory alignment.
- SONET/SDH functionality (family-level) — Family documentation describes built-in SONET scrambler/descrambler, streamlined SONET framing and limited Transport OverHead (TOH) handling suitable for SONET backplane implementations when used with protocol logic.
Typical Applications
- Telecom backplanes — Implement high-speed SONET/SDH or non-SONET backplane interfaces using integrated SERDES channels and programmable framing logic.
- Switch fabric interconnects — Support board-to-board high-throughput links for work and protection paths in line-card to fabric connections.
- High-speed data transport — Provide aggregated multi-gigabit backplane links and protocol termination with on-chip logic for packet or cell processing.
Unique Advantages
- Integrated high-speed transceivers: Eight 0.6–2.7 Gbps SERDES channels with CDR reduce external PHY requirements and simplify timing distribution across boards and backplanes.
- Substantial programmable fabric: 10,368 logic elements and an estimated system gate range suitable for implementing protocol engines, framers, and custom datapaths on-chip.
- High pin count and compact package: 372 user I/Os in a 680-FPBGA (35 × 35 mm) package enable dense system routing and flexible I/O assignments.
- Embedded memory accessibility: On-chip RAM (113,664 bits) plus embedded core RAM blocks accessible to FPGA logic help support buffering, FIFOs, and state storage without external memory.
- Flexible power options: Broad supply voltage support from 1.425 V to 3.6 V accommodates diverse system power architectures.
- Commercial-grade and RoHS compliant: Rated for 0 °C to 70 °C operation and RoHS-compliant, aligning with commercial telecom and networking equipment requirements.
Why Choose ORSO82G5-1FN680C?
The ORSO82G5-1FN680C positions itself as a high-density, high-speed FPGA solution for designers building backplane and board-to-board interfaces. With eight integrated SERDES channels, built-in CDR, extensive I/O, and a sizable logic fabric, it enables consolidation of protocol termination, framing and custom processing into a single surface-mount package.
This device is suited for telecommunications and networking applications that require configurable high-throughput links combined with programmable logic. Supported by the family documentation and development resources referenced in the product literature, the ORSO82G5-1FN680C offers a path to scalable, integrated designs for commercial networking equipment.
Request a quote or submit an inquiry to receive pricing and availability for ORSO82G5-1FN680C and discuss how it can fit into your next high-speed backplane or switch fabric design.

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