IS43R16320D-6TLI

IC DRAM 512MBIT PAR 66TSOP II
Part Description

IC DRAM 512MBIT PAR 66TSOP II

Quantity 139 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerIntegrated Silicon Solution Inc
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package66-TSOP IIMemory FormatDRAMTechnologySDRAM - DDR
Memory Size512 MbitAccess Time700 psGradeIndustrial
Clock Frequency166 MHzVoltage2.3V ~ 2.7VMemory TypeVolatile
Operating Temperature-40°C ~ 85°C (TA)Write Cycle Time Word Page15 nsPackaging66-TSSOP (0.400", 10.16mm Width)
Mounting MethodVolatileMemory InterfaceParallelMemory Organization32M x 16
Moisture Sensitivity Level3 (168 Hours)RoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
QualificationN/AECCNEAR99HTS Code8542.32.0028

Overview of IS43R16320D-6TLI – IC DRAM 512MBIT PAR 66TSOP II

The IS43R16320D-6TLI is a 512Mbit DDR SDRAM organized as 32M × 16, implemented in a parallel memory interface. It uses double-data-rate architecture with SSTL_2-compatible I/O and a differential clock scheme to support high-throughput read/write burst operations.

Designed for systems requiring a compact 66‑TSOP II footprint and industrial temperature range, the device offers programmable burst lengths and CAS latency options to match a range of performance and timing requirements.

Key Features

  • DDR SDRAM Core  Double-data-rate architecture with two data transfers per clock cycle and bidirectional data strobe (DQS) for accurate data capture.
  • Memory Organization  512 Mbit capacity organized as 32M × 16 with four internal banks to enable concurrent operations and burst access.
  • Clock and Timing  Differential clock inputs (CK and CK̅) and an internal DLL that aligns DQ/DQS with CK; supported clock frequency up to 166 MHz for the -6 speed grade and access time of 700 ps.
  • Burst and Latency Options  Burst length selectable (2, 4, 8) with sequential and interleave burst types and programmable CAS latency (2, 2.5, 3) to tune throughput and latency trade-offs.
  • Write and Data Masking  Data Mask (DM) masks write data on both edges of DQS; write cycle time (word/page) specified at 15 ns.
  • Refresh and Power Modes  Auto Refresh and Self Refresh modes supported for retained data during low-power intervals.
  • Voltage and I/O Standard  VDD/VDDQ operating range 2.3 V to 2.7 V and SSTL_2 compatible I/O signaling.
  • Package and Temperature  Available in a 66‑TSSOP (0.400", 10.16 mm width) TSOP‑II package and rated for -40 °C to +85 °C ambient operating temperature.

Typical Applications

  • Parallel memory subsystems  As a 32‑bit‑organized DDR SDRAM component for systems needing parallel high-speed buffering and burst data transfers.
  • Embedded platforms  For embedded designs requiring 512 Mbit of volatile DDR storage with selectable burst lengths and CAS latency.
  • Compact form-factor boards  Suited to designs constrained to a 66‑TSOP II package while maintaining DDR performance and industrial temperature support.

Unique Advantages

  • Flexible timing configuration: Programmable CAS latency (2, 2.5, 3) and selectable burst lengths allow designers to match memory timing to system requirements.
  • High effective data rate: Double-data-rate operation with edge-aligned DQS and DLL alignment improves data capture accuracy across both clock edges.
  • Compact package footprint: 66‑TSSOP (TSOP‑II) package provides a small board area for systems where PCB real estate is limited.
  • Industrial temperature range: Rated for -40 °C to +85 °C to support deployments that require extended ambient temperature operation.
  • SSTL_2 compatible I/O: Voltage and signaling compatibility for systems using SSTL_2 interfaces with VDD/VDDQ between 2.3 V and 2.7 V.

Why Choose IC DRAM 512MBIT PAR 66TSOP II?

The IS43R16320D-6TLI combines DDR SDRAM architecture, selectable timing parameters and a compact 66‑TSOP II package to deliver a configurable 512 Mbit parallel memory option. Its four internal banks, burst support and SSTL_2 I/O enable designers to balance throughput and latency according to system needs.

This part is appropriate for designs that require a compact, industrial‑temperature DDR memory device with flexible timing and refresh capabilities, providing predictable performance and integration in parallel memory subsystems.

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