IS46R16160D-5TLA1-TR

IC DRAM 256MBIT PAR 66TSOP II
Part Description

IC DRAM 256MBIT PAR 66TSOP II

Quantity 464 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerIntegrated Silicon Solution Inc
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package66-TSOP IIMemory FormatDRAMTechnologySDRAM - DDR
Memory Size256 MbitAccess Time700 psGradeIndustrial
Clock Frequency200 MHzVoltage2.3V ~ 2.7VMemory TypeVolatile
Operating Temperature-40°C ~ 85°C (TA)Write Cycle Time Word Page15 nsPackaging66-TSSOP (0.400", 10.16mm Width)
Mounting MethodVolatileMemory InterfaceParallelMemory Organization16M x 16
Moisture Sensitivity Level3 (168 Hours)RoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
QualificationN/AECCNEAR99HTS Code8542.32.0024

Overview of IS46R16160D-5TLA1-TR – IC DRAM 256MBIT PAR 66TSOP II

The IS46R16160D-5TLA1-TR is a 256 Mbit DDR SDRAM device from Integrated Silicon Solution Inc (ISSI) organized as 16M × 16 with a parallel memory interface. It implements double-data-rate architecture with a pipeline and four internal banks to support high-speed burst read/write operations and concurrent bank activity.

Targeted at systems that require volatile, high-throughput memory, the device delivers up to 200 MHz clock operation, SSTL_2 compatible I/O, programmable CAS latencies, and support for auto-refresh and self-refresh modes for reliable operation across -40°C to +85°C.

Key Features

  • Core architecture  Double-data-rate (DDR) pipeline design enabling two data transfers per clock cycle and four internal banks for concurrent operations.
  • Memory organization  256 Mbit capacity arranged as 16M × 16, providing a 16-bit data path and internal banked structure for efficient burst access.
  • Performance  Supports up to 200 MHz clock frequency (speed grade -5) with an access time of 700 ps and write cycle time (word/page) of 15 ns for high-throughput applications.
  • Interfaces and I/O  SSTL_2 compatible I/O, differential clock inputs (CK/CK̄), and bidirectional data strobe (DQS) for edge-aligned READ and centre-aligned WRITE capture.
  • Timing and programmability  Programmable CAS latencies of 2, 2.5 and 3; burst lengths of 2, 4 and 8; burst type selectable between sequential and interleave modes.
  • Refresh and power modes  Auto Refresh and Self Refresh modes plus Auto Precharge; VDD and VDDQ nominal 2.5V (2.3V–2.7V supply range).
  • Package and mounting  Supplied in a 66-pin TSOP-II (66-TSSOP) package with 0.400" (10.16 mm) width for surface-mount assembly.
  • Operating temperature  Industrial temperature range specified at -40°C to +85°C (TA).

Typical Applications

  • High-speed data buffering  Use where high-throughput burst reads/writes are required; DDR architecture and pipeline operation support continuous burst transfers.
  • Embedded memory subsystems  Suitable for embedded platforms needing a 16-bit parallel DDR memory with programmable CAS latency and selectable burst lengths.
  • Systems with extended temperature requirements  Applicable in designs requiring reliable DDR operation across -40°C to +85°C.

Unique Advantages

  • Double-data-rate transfers: Two data transfers per clock cycle increase effective bandwidth without raising clock frequency.
  • SSTL_2 compatible I/O: Ensures compatibility with SSTL_2 signaling environments for predictable interface behavior.
  • Flexible timing and bursts: Programmable CAS latencies and selectable burst lengths allow tuning for system trade-offs between latency and throughput.
  • Banked architecture: Four internal banks enable concurrent operations and reduce effective access contention for bursty workloads.
  • Industrial temperature rating: Specified operation from -40°C to +85°C supports deployment in temperature-sensitive applications.
  • Compact surface-mount package: 66-TSSOP package provides a low-profile, PCB-friendly footprint for space-constrained designs.

Why Choose IS46R16160D-5TLA1-TR?

The IS46R16160D-5TLA1-TR combines DDR pipeline architecture, programmable timing, and SSTL_2 I/O in a 256 Mbit, 16-bit parallel configuration to meet the needs of systems that demand burst-capable volatile memory. Its 200 MHz speed grade, four-bank organization and refresh/self-refresh support make it suitable for designs that prioritize steady high-throughput and predictable timing behavior.

Manufactured by ISSI and available in a 66-pin TSOP-II package with industrial temperature range and a 2.3V–2.7V supply window, this device is appropriate for engineers seeking a compact DDR SDRAM solution with configurable latency and burst options for embedded and high-performance memory subsystems.

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