LFE3-35EA-8LFN672I

IC FPGA 310 I/O 672FPBGA
Part Description

ECP3 Field Programmable Gate Array (FPGA) IC 310 1358848 33000 672-BBGA

Quantity 1,997 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time20 Weeks
Datasheet

Specifications & Environmental

Device Package672-FPBGA (27x27)GradeIndustrialOperating Temperature-40°C – 100°C
Package / Case672-BBGANumber of I/O310Voltage1.14 V - 1.26 V
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs4125Number of Logic Elements/Cells33000
Number of GatesN/AECCN3A991DHTS Code8542.39.0001
QualificationN/ATotal RAM Bits1358848

Overview of LFE3-35EA-8LFN672I – ECP3 FPGA, 33,000 logic elements, 310 I/Os

The LFE3-35EA-8LFN672I is an ECP3 family Field Programmable Gate Array (FPGA) from Lattice Semiconductor Corporation designed for high-density, cost-sensitive system integration. This device combines a dense logic fabric, embedded memory, and flexible I/O in a 672‑ball BGA package for industrial applications requiring wide temperature operation.

Built on the Lattice ECP3 architecture, the device targets high-volume, high-speed, low-cost applications and provides on-chip resources for DSP, SERDES, and source-synchronous interfaces to simplify system design and integration.

Key Features

  • Logic Capacity — 33,000 logic elements provide a substantial programmable fabric for mid-range FPGA designs.
  • Embedded Memory — Approximately 1.36 Mbits of on-chip RAM (1,358,848 total RAM bits) for buffering, frame storage, and local data processing.
  • I/O Density — 310 user I/Os in the 672‑ball package to support complex multi-interface systems and external peripherals.
  • High‑speed SERDES — Family-level embedded SERDES support up to 3.2 Gbps; the ECP3-35 in the 672 package is listed with 4 SERDES channels alongside 310 I/Os.
  • DSP and Arithmetic Acceleration — ECP3 family sysDSP architecture provides cascaded DSP slices and multiply/accumulate resources for high-performance signal processing (family feature).
  • Clocking and Timing — On-chip PLLs and DLLs (family feature) for flexible clock management and source‑synchronous interface support.
  • Configurable I/O Standards — Programmable sysI/O buffer support for a wide range of I/O standards and optional on‑chip termination (family feature).
  • Power — Core voltage specified between 1.14 V and 1.26 V with a nominal 1.2 V core supply on the ECP3 family.
  • Package and Thermal — 672‑ball BGA (supplier package 672‑FPBGA, 27 × 27 mm) with industrial operating temperature from −40 °C to 100 °C.
  • Standards & Tools — Device family includes system-level support such as IEEE 1149.1/1532 compatibility and configuration utilities (family feature).
  • RoHS Compliant — Meets RoHS environmental requirements.

Typical Applications

  • Communications Equipment — Implement protocol bridging, SERDES interfacing, and packet processing using on‑chip SERDES and DSP resources.
  • Industrial Control — Deploy control logic, sensor aggregation, and deterministic I/O handling across wide temperature ranges using the industrial-grade device.
  • Video and Imaging — Use embedded memory and DSP slices for frame buffering, pre-processing, and data formatting in video pipelines.
  • Interface Aggregation — Consolidate multiple parallel and serial interfaces with the device’s high I/O count and programmable I/O buffers.

Unique Advantages

  • Highly Integrated Mid‑Range FPGA: Combines 33,000 logic elements with ~1.36 Mbits of embedded RAM and 310 I/Os to reduce external component count.
  • Flexible High‑Speed Connectivity: Family SERDES capability (up to 3.2 Gbps) and the 672‑ball package mapping enable multi‑channel serial links alongside abundant GPIO.
  • Industrial Temperature Support: Qualified for −40 °C to 100 °C operation to meet demanding environmental requirements.
  • Configurable I/O and Clocking: Programmable sysI/O buffers, on‑chip termination options, and multiple PLL/DLL resources help match diverse interface and timing needs.
  • Proven Ecosystem: ECP3 family tooling and system features for configuration, debugging, and analysis streamline development and deployment.

Why Choose LFE3-35EA-8LFN672I?

The LFE3-35EA-8LFN672I positions itself as a versatile mid-range FPGA that balances programmable logic density, embedded memory, and high I/O count in a single industrial-grade package. It is suited to customers needing a scalable, integrated solution for communications, industrial control, and imaging applications where SERDES, DSP acceleration, and robust I/O are required.

Choosing this ECP3 device provides a combination of field-proven family features, industrial temperature capability, and a compact 672‑ball BGA package to help reduce board-level complexity while supporting a wide range of system interfaces.

Request a quote or submit an inquiry to obtain pricing and availability for LFE3-35EA-8LFN672I. Include your required quantity and any delivery or configuration notes to expedite processing.

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