H54G46CYRBX267

The H54G46CYRBX267 is an SK hynix 2 GB dual-mode LPDDR4/LPDDR4X SDRAM supporting both standards in a single device. Organized as a dual-channel, single-chip-select device (2CH 1CS), each channel on an 8 Gb × 16 die delivers up to 4266 Mbps over a 16-bit data bus — offering design flexibility for platforms targeting either LPDDR4 or LPDDR4X interfaces.

In LPDDR4 mode VDD2 and VDDQ operate at a combined 1.1V; in LPDDR4X mode VDDQ drops to 0.6V for lower I/O power. This low power DRAM is JEDEC-compliant, RoHS compliant, lead-free, and halogen-free in a 200-ball FBGA (10 mm × 15 mm) for commercial −25°C to 85°C operation.

Key Features

• Dual-Mode LPDDR4 and LPDDR4X in One Device
  Supports both LPDDR4 (VDD2/VDDQ = 1.1V) and LPDDR4X (VDDQ = 0.6V) operation, allowing one part to serve LPDDR4 and LPDDR4X designs and simplifying procurement and SKU management.
• 4266 Mbps Double-Data-Rate Interface
  Two data accesses per clock cycle at up to 4266 Mbps (tCK(avg) min = 0.468 ns); single-data-rate command/address over 6-bit CA bus; differential clock CK_t/CK_c and bi-directional differential strobes DQS_t/DQS_c.
• Dual-Channel x16 Architecture — 2 GB
  Two independent 8 Gb × 16 channels each with 16-bit bus DQ[15:0], differential strobe pairs DQS[1:0]_t/_c, and two DMI pins per channel for write data masking and Data Bus Inversion (DBIdc).
• Flexible Dual Voltage Supply
  LPDDR4: VDD1 = 1.8V (1.70V–1.95V), VDD2 = VDDQ = 1.1V (1.06V–1.17V). LPDDR4X: VDD1 = 1.8V, VDD2 = 1.1V, VDDQ = 0.6V (0.57V–0.65V) for lower I/O power in mobile SoC and embedded DRAM platforms.
• Programmable ODT, ZQ Calibration, and Burst Control
  Programmable CA ODT and DQ ODT with VSSQ termination (MR11, MR22); DQ ODT RZQ/1–RZQ/6 (240Ω–40Ω) with VOH-compensated output driver; background ZQ calibration; burst length 16 (default), 32, and on-the-fly; programmable RL/WL across FSP[0] and FSP[1].
• Advanced Refresh — Auto TCSR, Per-Bank, and PASR
  All-bank and directed per-bank auto refresh; Auto Temperature Compensated Self Refresh (Auto TCSR); Partial Array Self Refresh (PASR) with bank mask (MR16) and segment mask (MR17) to minimize refresh area and standby power.
• 200-Ball FBGA — 10 mm × 15 mm, RoHS, Lead-Free, Halogen-Free
  0.80/0.65 mm pitch, 1.00 mm max height; RoHS compliant, lead-free, halogen-free LPDDR4/LPDDR4X BGA for space-constrained consumer and embedded board designs.

Typical Applications

• Mobile SoCs and Consumer Electronics
  4266 Mbps dual-channel bandwidth and dual LPDDR4/LPDDR4X compatibility suit mobile application processors, smartphones, tablets, and consumer devices where interface flexibility and throughput are priorities.
• Embedded Computing and Industrial IoT
  PASR, Auto TCSR, and −25°C to 85°C range support embedded DRAM in industrial IoT gateways, networking equipment, and edge computing nodes needing low power DRAM.
• Communications and Networking
  Dual-mode support and high-bandwidth dual-channel architecture suit network processors, wireless infrastructure, and communications SoCs requiring high-throughput memory.

Unique Advantages

• One part covers both LPDDR4 and LPDDR4X designs: Dual-mode operation reduces SKU complexity, simplifying supply chain and platform reuse across LPDDR4 and LPDDR4X systems.
• Frequency Set Point (FSP) switching: Dual FSPs enable atomic switch of timing, ODT, and Vref via a single MRW command for zero-gap DVFS in mobile and embedded SoCs.
• On-chip DQS Interval Oscillator: Tracks DQS delay drift for adaptive re-training only when needed, reducing system overhead.
• Post Package Repair (PPR): Electrical-fuse-based repair of one failed row per bank per channel enables field yield recovery without package replacement.

Why Choose H54G46CYRBX267?

The H54G46CYRBX267 combines SK hynix LPDDR4/LPDDR4X dual-mode memory with 4266 Mbps dual-channel bandwidth, flexible 1.1V/0.6V VDDQ supply, PASR, Auto TCSR, FSP switching, and Post Package Repair in a 200-ball FBGA — a versatile low power DRAM solution for consumer electronics, embedded computing, industrial IoT, and communications platforms requiring LPDDR4 or LPDDR4X compatibility.

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