IS43R16160B-5TLI-TR

IC DRAM 256MBIT PAR 66TSOP II
Part Description

IC DRAM 256MBIT PAR 66TSOP II

Quantity 46 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerIntegrated Silicon Solution Inc
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package66-TSOP IIMemory FormatDRAMTechnologySDRAM - DDR
Memory Size256 MbitAccess Time700 psGradeIndustrial
Clock Frequency200 MHzVoltage2.3V ~ 2.7VMemory TypeVolatile
Operating Temperature-40°C ~ 85°C (TA)Write Cycle Time Word Page15 nsPackaging66-TSSOP (0.400", 10.16mm Width)
Mounting MethodVolatileMemory InterfaceParallelMemory Organization16M x 16
Moisture Sensitivity Level3 (168 Hours)RoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
QualificationN/AECCNEAR99HTS Code8542.32.0024

Overview of IS43R16160B-5TLI-TR – IC DRAM 256MBIT PAR 66TSOP II

The IS43R16160B-5TLI-TR is a 256 Mbit double data rate (DDR) synchronous DRAM organized as 16M × 16 with a parallel interface. It implements a 4-bank DDR architecture with SSTL_2 signaling, differential clock inputs and on-die DLL to align data and strobe timing.

Designed for applications that require high-speed parallel DRAM, the device delivers up to 200 MHz clock operation with programmable CAS latency and burst length options, while supporting industrial operating temperatures and compact board-level packaging.

Key Features

  • Core & Architecture  DDR synchronous DRAM with double data rate transfers and a 4-bank organization (4,194,304-word × 16). On-die DLL aligns DQ and DQS transitions with CLK edges.
  • Memory Capacity & Organization  256 Mbit total memory, organized as 16M × 16, supporting burst lengths of 2/4/8 and programmable burst type (Sequential/Interleave).
  • Performance  Clock rate up to 200 MHz with programmable CAS latency (2.0, 2.5, 3.0) and access timing with typical ±0.70 ns access time; write cycle (word/page) time 15 ns.
  • Interface & Timing  Parallel memory interface with bidirectional data strobe (DQS), differential clock inputs (CLK and /CLK) and SSTL_2 signaling. Commands enter on CLK rising edge; data referenced to both edges of DQS.
  • Power & Supply  VDD and VDDQ centered on 2.5 V (VDD = VDDQ = 2.5 V ±0.2 V) with an operating supply range specified as 2.3 V to 2.7 V.
  • Refresh & Reliability Features  Supports auto refresh and self refresh with 8,192 refresh cycles per 64 ms and options for auto-precharge/all-bank precharge control via address inputs.
  • Package & Mounting  Available in a 66-pin TSOP II (66-TSSOP, 0.400", 10.16 mm width) package for compact board-level integration.
  • Operating Temperature  Specified to operate from -40°C to +85°C (TA), covering extended-temperature applications.

Typical Applications

  • High-speed system memory  Use as working memory where DDR transfers and up to 200 MHz clock rates are required for fast data throughput.
  • Parallel bus DRAM  Designed for designs that require a 16-bit parallel memory interface with programmable burst and CAS latency.
  • Industrial-temperature designs  Suitable for systems that must operate across an extended temperature range (-40°C to +85°C).
  • Board-level compact memory  Compact 66-TSOP II package enables dense memory implementation on space-constrained PCBs.

Unique Advantages

  • DDR data-rate efficiency: Double data rate architecture provides two data transfers per clock cycle, increasing data throughput without raising clock frequency.
  • Flexible performance tuning: Programmable CAS latency (2.0/2.5/3.0) and burst length choices allow designers to balance latency and bandwidth for target systems.
  • SSTL_2 and differential clock support: Differential CLK/ /CLK and SSTL_2 signaling improve timing robustness for high-speed parallel interfaces.
  • Robust refresh management: Auto-refresh and self-refresh support plus 8,192 refresh cycles per 64 ms simplify memory maintenance and reliability.
  • Compact package for dense boards: 66-TSSOP (TSOP II) package offers a small footprint for board-level memory expansion.
  • Extended temperature operation: Specified operation from -40°C to +85°C supports use in thermally demanding environments.

Why Choose IC DRAM 256MBIT PAR 66TSOP II?

The IS43R16160B-5TLI-TR combines DDR synchronous DRAM architecture, flexible timing options and SSTL_2-compatible signaling to deliver high-speed parallel memory in a compact 66-TSOP II footprint. Its programmable CAS latency, burst modes and on-die DLL facilitate precise timing alignment for demanding memory subsystems.

This device is appropriate for designs that need 256 Mbit of parallel DDR memory with up to 200 MHz clock operation and extended-temperature capability, offering configurability and compact packaging for embedded and board-level memory solutions.

Request a quote or submit an inquiry for IS43R16160B-5TLI-TR to obtain pricing, availability and technical support information tailored to your design requirements.

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