M13S128168A-5TG2S
| Part Description |
DDR SDRAM 128Mbit 2Mx16 200MHz 66-TSOPII Commercial |
|---|---|
| Quantity | 1,387 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 66-TSOPII | Memory Format | DRAM | Technology | DRAM | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 128 Mbit | Access Time | 15 ns | Grade | Commercial | ||
| Clock Frequency | 200 MHz | Voltage | 2.3V ~ 2.7V | Memory Type | Volatile | ||
| Operating Temperature | 0°C – 70°C | Write Cycle Time Word Page | 15 ns | Packaging | 66-TSOPII | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 2M x 16 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | JEDEC | ECCN | EAR99 | HTS Code | 8542.32.00.02 |
Overview of M13S128168A-5TG2S – DDR SDRAM 128Mbit 2Mx16 200MHz 66-TSOPII Commercial
The M13S128168A-5TG2S is a commercial-grade DDR SDRAM device organized as 2M × 16, delivering a nominal 128Mbit memory capacity and rated for a 200 MHz clock (DDR400 operation). It implements a double-data-rate architecture with four internal banks and supports standard DDR features for system memory expansion in designs requiring parallel DDR interfaces.
Designed for surface-mount implementation in a 66-pin TSOPII package, this JEDEC-qualified, RoHS-compliant device targets applications that require low-voltage 2.5V-class DDR operation, precise timing options, and standard DDR signaling (SSTL_2 compatible).
Key Features
- DDR Architecture Double-data-rate operation with data transfers on both clock edges and a DLL to align DQ/DQS timing for robust read/write timing.
- Memory Organization 2M × 16 organization providing a 128Mbit nominal density (specification lists 134.2 Mbit memory size) with four-bank operation to support standard DDR access patterns.
- Performance and Timing Rated for 200 MHz clock frequency (DDR400), with access time and write cycle time listed at 15 ns and supported CAS latencies of 2, 2.5 and 3. Burst lengths of 2, 4 and 8 and both sequential and interleave burst types are supported.
- Interface and Signaling Parallel DDR interface with differential clock inputs (CLK/CLK¯), bi-directional data strobes (DQS), and SSTL_2-compatible 2.5V I/O signaling (VDD/VDDQ = 2.5V ±0.2V).
- Power and Refresh Low-voltage DDR operation with VDD/VDDQ in the 2.3–2.7 V range and built-in refresh support including auto and self-refresh with a 15.6 µs refresh interval.
- Package and Mounting 66-pin TSOPII surface-mount package (400 mil × 875 mil body, 0.65 mm pin pitch) optimized for PCB-mounted memory implementations.
- Commercial Temperature Range Specified operating ambient temperature from 0 °C to +70 °C for commercial applications.
- Standards and Compliance JEDEC-qualified device with RoHS compliance for regulatory and environmental conformity.
Typical Applications
- DDR400-class System Memory Implement parallel DDR memory expansion where a 2M × 16, 200 MHz DDR SDRAM device is required for buffering or working memory.
- FPGA and ASIC Memory Interfaces Use as external DDR memory for FPGA/ASIC designs requiring SSTL_2-compatible 2.5V I/O and standard DDR signaling (DQS, differential CLK).
- Embedded and Consumer Electronics Suitable for commercial embedded platforms and consumer devices that operate within the 0 °C to 70 °C range and require JEDEC-standard DDR operation.
Unique Advantages
- Standard DDR Feature Set: CAS latency options, multi-bank operation, DLL alignment and DQS support enable predictable DDR timing for established memory controllers.
- SSTL_2-Compatible I/O: 2.5V I/O signaling (VDD/VDDQ = 2.5V ±0.2V) simplifies integration with common DDR memory interfaces and controllers.
- Flexible Burst and Latency Options: Support for burst lengths of 2/4/8 and CAS latencies 2/2.5/3 enables tuning for throughput versus latency trade-offs in system design.
- Compact TSOPII Package: 66-pin TSOPII surface-mount package provides a compact PCB footprint for space-constrained applications.
- JEDEC and RoHS Compliance: JEDEC qualification and RoHS compliance aid in regulatory alignment and streamlined procurement for commercial products.
Why Choose M13S128168A-5TG2S?
The M13S128168A-5TG2S offers a straightforward, JEDEC-standard DDR SDRAM solution with 2M × 16 organization, DDR400-rated timing, and a TSOPII surface-mount package for compact board-level integration. Its combination of standard DDR features (DLL, DQS, CAS latency options) and SSTL_2-compatible signaling makes it suitable for designs requiring predictable DDR behavior and 2.5V I/O operation.
This device is well-suited for engineers and procurements targeting commercial-grade memory for embedded systems, FPGA/ASIC interfaces, and other DDR-capable platforms that operate within the 0 °C to +70 °C range and require JEDEC-compliant DDR memory behavior.
Request a quote or submit a procurement inquiry to receive pricing and availability information for M13S128168A-5TG2S.
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