M15T1G1664A (2S)
| Part Description |
DDRIII SDRAM 1.35V/ 1.5V |
|---|---|
| Quantity | 1,147 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 96 BAll BGA | Memory Format | DRAM | Technology | DDR3 SDRAM | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 1 Gbit | Access Time | 13.91 ns | Grade | Commercial | ||
| Clock Frequency | 1.066 GHz | Voltage | 1.5V | Memory Type | Volatile | ||
| Operating Temperature | 0°C – 85°C | Write Cycle Time Word Page | 15 ns | Packaging | 96 BAll BGA | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 64M x 16 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | JEDEC | ECCN | EAR99 | HTS Code | 8542.32.00.32 |
Overview of M15T1G1664A (2S) – DDRIII SDRAM 1.35V/ 1.5V
The M15T1G1664A (2S) is a 1.074 Gbit DDR3(L) SDRAM organized as 64M × 16 with eight internal banks and an 8n prefetch architecture. It provides synchronized, double-data-rate transfers with differential clock and data-strobe signaling and is JEDEC DDR3(L) compliant.
Targeted for commercial systems and general applications that require high-speed, low-latency volatile memory, this surface-mount 96-ball BGA device supports dual supply options (1.35V and 1.5V) and transfer rates up to DDR3(L)-2133 for demanding memory subsystems.
Key Features
- Memory Core 1.074 Gbit density organized as 64M × 16 across 8 banks with 8n prefetch architecture for high-throughput DDR operation.
- Performance Supports clock operation to 1.066 GHz (1066 MHz) and data rates up to DDR3(L)-2133 (14-14-14 timing option listed), with typical access time of 13.91 ns and write cycle time (word/page) of 15 ns.
- Interface & Power Dual supply support via SSTL_135 (VDD/VDDQ = 1.35V) and SSTL_15 (VDD/VDDQ = 1.5V) allowing flexible system voltage choices within JEDEC tolerances.
- Synchronous Signaling Differential CK/CK and DQS/DQS pairs with source-synchronous DQS, and double-data-rate transfers on DQ, DQS and DM for reliable high-speed timing.
- Signal Integrity & Calibration Configurable drive strength and on-die termination (RTT), plus ZQ calibration (external ZQ pad) for DS/ODT impedance accuracy.
- Data Integrity & Power Management Supports Auto Refresh and Self Refresh modes, Partial Array Self Refresh (PASR), and Power Down mode to manage data retention and power consumption.
- Programmability Wide range of programmable timings and behaviors including CAS latencies (6–14), CAS write latencies, additive latency options, write recovery times, burst formats and on-die termination settings.
- Package & Thermal Surface-mount 96-ball BGA package with commercial operating temperature range of 0°C to 85°C; JEDEC-qualified for standard commercial designs.
- Compliance JEDEC DDR3(L) compliant and RoHS compliant.
Typical Applications
- General computing systems — Acts as synchronous DDR3(L) memory for systems that require up to DDR3(L)-2133 transfer rates and JEDEC-compliant operation.
- Memory subsystems — Suitable for integration into memory modules and board-level DRAM subsystems where 1Gb density and 64M × 16 organization are required.
- Commercial embedded electronics — Provides high-speed volatile memory for commercial-grade products with an operating temperature range of 0°C to 85°C.
Unique Advantages
- Dual-voltage support: Operates at both 1.35V and 1.5V (SSTL_135 / SSTL_15) to match system power profiles and design constraints.
- High throughput capability: 8n prefetch architecture and support for DDR3(L)-2133 data rates enable high-bandwidth memory transfers.
- Robust signal control: Configurable drive strengths, on-die termination options and ZQ calibration help maintain signal integrity across platforms.
- Flexible timing programmability: Extensive CAS and timing options allow designers to tune performance and latency to system requirements.
- Compact board footprint: 96-ball BGA surface-mount package supports dense board layouts and automated assembly processes.
- Standards-based compliance: JEDEC DDR3(L) compliance and RoHS conformity simplify qualification for commercial designs.
Why Choose M15T1G1664A (2S)?
The M15T1G1664A (2S) delivers a standards-compliant, high-throughput DDR3(L) memory option in a compact 96-ball BGA footprint. With dual-voltage operation, configurable termination and calibration features, and extensive timing programmability, it fits commercial systems that require reliable, tunable DRAM performance.
This part is well suited for designers building JEDEC-compliant memory subsystems who need 1Gb density with up to DDR3(L)-2133 transfer capability, commercial-grade temperature range, and surface-mount packaging for automated assembly and compact layouts.
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Date Founded: 1998
Headquarters: Hsinchu Science Park, Hsinchu, Taiwan
Employees: 400+
Revenue: $377.8 Million
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