M15T2G16128A-EFBG2D
| Part Description |
DDR3L SDRAM 2Gb 128M × 16 1066MHz 96-Ball BGA |
|---|---|
| Quantity | 1,293 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 96 Ball BGA | Memory Format | DRAM | Technology | DDR3L | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 2 Gbit | Access Time | 13.91 ns | Grade | Industrial | ||
| Clock Frequency | 1.066 GHz | Voltage | 1.35V, 1.5V | Memory Type | Volatile | ||
| Operating Temperature | -40°C – 95°C | Write Cycle Time Word Page | 15 ns | Packaging | 96 Ball BGA | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 128M x 16 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | JEDEC | ECCN | EAR99 | HTS Code | 8542.32.00.36 |
Overview of M15T2G16128A-EFBG2D – DDR3L SDRAM 2Gb 128M × 16 1066MHz 96-Ball BGA
The M15T2G16128A-EFBG2D is a 2Gb DDR3(L) SDRAM device organized as 128M × 16 with an eight-bank architecture. It delivers double-data-rate transfers and supports DDR3(L)-2133 operation to address high-density memory requirements in industrial and general applications.
Designed for board-level integration, this JEDEC-compliant device supports both 1.35V and 1.5V supply options, a 96-ball BGA package, and an extended operating temperature range for industrial deployments.
Key Features
- Memory Architecture 2.147 Gbit density organized as 128M × 16 with 8 banks and a 2KB page size per bank.
- Performance 1.066 GHz clock frequency supporting DDR3(L)-2133 data rate; documented access time 13.91 ns and write cycle time (word page) 15 ns.
- Interface and Timing Differential clock (CK/CK) and data strobe (DQS/DQS), double-data-rate on DQs/DQS/DM, configurable CAS latencies and programmable burst length/type. CAS Latency options include 5–14; CAS write latency and additive latency are supported per MR settings.
- Power and Voltage Supports SSTL_135 (VDD/VDDQ = 1.35V) and SSTL_15 (VDD/VDDQ = 1.5V). Features include auto refresh, self refresh, power down, partial array self refresh (PASR) and programmable power-saving modes.
- Signal Integrity and Calibration Configurable drive strength (DS), configurable On-Die Termination (ODT) with RTT_Nom and RTT_WR options, and ZQ calibration for DS/ODT impedance accuracy via external ZQ pad.
- Read/Write Leveling and Programmability Write leveling via mode register settings and read leveling via MPR, plus programmable write recovery, burst control and precharge power-down behavior.
- Package and Mounting Surface-mount 96 ball BGA package optimized for compact board layouts and high-density memory designs.
- Qualification and Environmental JEDEC DDR3(L) compliant, industrial grade with operating temperature −40°C to 95°C, and RoHS compliant.
Typical Applications
- Industrial Systems Use in industrial controllers and equipment where JEDEC compliance and an extended −40°C to 95°C operating range are required.
- General-Purpose Computing Memory expansion for general applications requiring high-density DDR3(L) storage and standard DDR3 feature sets.
- Embedded Memory Modules Integration into compact module designs that require a 2Gb DDR3(L) device in a 96-ball BGA footprint.
- Board-Level High-Density Memory Suitable for designs needing a 128M × 16 organization with programmable timing and signal-integrity controls.
Unique Advantages
- Dual-voltage compatibility: Supports both 1.35V and 1.5V operation (SSTL_135 and SSTL_15) for flexibility across system power domains.
- Wide operating range: Industrial-grade specification with −40°C to 95°C operating temperature for harsh-environment deployment.
- Extensive timing programmability: Multiple CAS latency, write latency and burst options enable tuning to system requirements.
- Signal-integrity controls: Configurable DS and On-Die Termination plus ZQ calibration improve impedance accuracy and system signal performance.
- Compact, high-density package: 2Gb capacity in a 96-ball BGA supports high-density board layouts.
- JEDEC compliance: Adherence to DDR3(L) JEDEC standards supports interoperability with standard DDR3 tooling and designs.
Why Choose M15T2G16128A-EFBG2D?
The M15T2G16128A-EFBG2D combines a 2Gb DDR3(L) density with flexible timing, dual-voltage operation and on-die termination/configuration features to support demanding industrial and general applications. JEDEC compliance and a compact 96-ball BGA package make it suitable for designers needing standardized, board-level memory building blocks.
Its programmable timing options, ZQ calibration and leveling features provide designers with the controls needed to match system timing and signal-integrity requirements while the wide operating temperature range and RoHS compliance align to industrial deployment needs.
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