M55D1G1664A-CDBIG2Y
| Part Description |
LPDDR3 SDRAM 1Gb 800MHz Industrial Grade |
|---|---|
| Quantity | 546 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 178-BGA (10x11.5) | Memory Format | DRAM | Technology | DRAM | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 1 Gbit | Access Time | 5.5 ns | Grade | Industrial | ||
| Clock Frequency | 800 MHz | Voltage | 1.14V ~ 1.30V, 1.70V ~ 1.95V | Memory Type | Volatile | ||
| Operating Temperature | -40°C – 85°C | Write Cycle Time Word Page | 15 ns | Packaging | 178-BGA | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 64M x 16 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | JEDEC | ECCN | EAR99 | HTS Code | 8542.32.00.32 |
Overview of M55D1G1664A-CDBIG2Y – LPDDR3 SDRAM 1Gb 800MHz Industrial Grade
The M55D1G1664A-CDBIG2Y is a JEDEC-compliant LPDDR3 SDRAM device delivering 1.074 Gbit organized as 64M × 16 with an 8-bank architecture. It provides low-voltage core and I/O operation, industrial temperature capability, and a compact 178-ball BGA package for board-level surface-mount integration.
Designed for industrial memory subsystems, the device combines double-data-rate performance at an 800 MHz clock (1600 Mb/s data rate) with LPDDR3 power domains and memory-management features to support embedded, low-voltage designs requiring stable operation from −40°C to 85°C.
Key Features
- Memory Organization — 1.074 Gbit capacity configured as 64M × 16 with eight internal banks (8M words × 16 bits × 8 banks) and a 4KB page size.
- Performance — 800 MHz clock frequency (1600 Mb/s data rate) with supported read latencies including RL up to 12 for this part and burst length BL = 8.
- Low-Voltage Power Domains — VDD1 (1.70–1.95V) for I/O and VDD2/VDDCA/VDDQ (1.14–1.30V) for core/I/O, enabling low-voltage system designs.
- Timing and Access — Access time 5.5 ns and write cycle time (word page) 15 ns as specified for device operation.
- LPDDR3 Interface and Training — JEDEC LPDDR3-compliant: DDR command/address inputs, differential clock inputs, DQS per byte, CA training and write leveling support.
- Power and Refresh — Auto refresh, self refresh, per-bank refresh, auto temperature compensated self refresh (ATCSR), and deep power-down (DPD) features for power-managed operation.
- Signal and Drive Options — On-die termination (ODT), programmable drive strength (DS), and data mask (DM) support for write data control.
- Package and Mounting — 178-ball BGA (10 × 11.5 mm ball grid) in a surface-mount form factor; Pb-free and RoHS compliant.
- Industrial Temperature Range — Rated for operation from −40°C to 85°C for industrial applications.
Typical Applications
- Industrial Embedded Systems — Provides industrial-temperature LPDDR3 memory capacity and low-voltage operation for embedded controllers and instrumentation.
- Board-Level Memory Expansion — 178-BGA surface-mount package suited for PCB memory subsystems where space and integration are important.
- Low-Voltage Designs — Dual-voltage domains (VDD1 and VDD2/VDDQ) support integration into low-power memory architectures.
- High-Performance Memory Subsystems — 800 MHz clock and 1600 Mb/s data rate for applications that require bandwidth within LPDDR3 performance envelopes.
Unique Advantages
- Industrial-Grade Reliability: Specified for −40°C to 85°C operation to meet industrial environment requirements.
- JEDEC LPDDR3 Compliance: Standardized LPDDR3 feature set including CA training, write leveling, and DQS per byte simplifies system integration.
- Low-Voltage Efficiency: Separate core and I/O voltage ranges (1.14–1.30V and 1.70–1.95V) enable energy-efficient memory operation.
- Flexible Power Management: Multiple refresh and low-power modes (self refresh, ATCSR, deep power-down) for optimized power profiles.
- Compact, Assembly-Ready Package: 178-ball BGA surface-mount package (10 × 11.5 mm) supports high-density board layouts and automated assembly.
Why Choose M55D1G1664A-CDBIG2Y?
The M55D1G1664A-CDBIG2Y positions LPDDR3 performance and industrial-grade robustness in a compact, surface-mount BGA package. With JEDEC LPDDR3 compliance, low-voltage power domains, and per-bank refresh and training features, it is suited to designs that require reliable memory operation across temperature extremes and power-managed modes.
This part is appropriate for teams specifying industrial memory capacity with predictable timing (access time 5.5 ns, write cycle 15 ns), 800 MHz clock operation, and the integration benefits of programmable drive strength, ODT, and training features to aid signal timing on board-level designs.
Request a quote or submit a procurement inquiry today to evaluate M55D1G1664A-CDBIG2Y for your next industrial LPDDR3 memory design.
Date Founded: 1998
Headquarters: Hsinchu Science Park, Hsinchu, Taiwan
Employees: 400+
Revenue: $377.8 Million
Certifications and Memberships: N/A